Nonlinear data conversion for multi-quadrant multiplication in artificial intelligence

ABSTRACT

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

The present disclosure claims priority from U.S. Provisional PatentApplication Ser. No. 62/856,889 filed Jun. 4, 2019 and which is hereinspecifically incorporated by reference in its entirety. Furthermore, thepresent disclosure claims priority from U.S. Provisional PatentApplication Ser. No. 62/880,885 filed Jul. 31, 2019 and which is hereinspecifically incorporated by reference in its entirety. Moreover, thepresent disclosure claims priority from U.S. Provisional PatentApplication Ser. No. 62/912,407 filed Oct. 8, 2019 and which is hereinspecifically incorporated by reference in its entirety. The presentdisclosure claims priority from U.S. Provisional Patent Application Ser.No. 62/865,845 filed Jun. 24, 2019 and which is herein specificallyincorporated by reference in its entirety. Furthermore, the presentdisclosure claims priority from U.S. Provisional Patent Application Ser.No. 62/862,772 filed Jun. 18, 2019 and which is herein specificallyincorporated by reference in its entirety. The present invention is acontinuation-in-part of and claims the benefit of priority from U.S.patent application Ser. No. 16/381,245 filed on Apr. 11, 2019; whichclaims priority from U.S. Provisional Patent Application Ser. No.62/658,678 filed on Apr. 17, 2018, and which are herein specificallyincorporated by reference in their entirety.

FIELD OF DISCLOSURE

This disclosure relates to improvements in mixed-signal data-converters,multipliers, and multiply-accumulate for use in integrated circuits(ICs) in general. The disclosure more specifically relates to emergingartificial intelligence and machine learning (AI & ML) applications thatare mobile, portable, and near edge and or on sensors, which requireultra-low-power, small-size, low cost (for high-volumes) andasynchronous operations.

BACKGROUND

One-size-fit-all and standard digital solutions for AI & ML applicationsoffer ease of interface compatibility, programming flexibility, and fasttime to market advantages. However, as AI & ML applications expand theirfoot-print closer to the edge of the network and or on intelligentsensors (where signals are gathered and processed together), moreapplication specific and custom solutions may be required to meetlow-power, low-cost, and high-volume objectives. Majority of digital AI& ML chips that are generally deployed on the cloud require bleedingedge deep sub-micron (e.g., 20 nano-meter and smaller) manufacturingwhich are expensive and power hungry. As such, to deploy AI &MLsolutions closer to the edge of communication networks or near sensorsand mobile devices, the high cost and high-power consumption of bleedingedge digital solutions become prohibitive. Approximate computing, thatcan utilize analog and mixed-signal processing, enables AI & MLsolutions including in for example in robotics, medical, mobile, drone,portable and private surveillance, and other near sensor applicationsthat need privacy, cannot afford latency, require low cost and low powerconsumption along with asynchronous signal processing. Moreover, cheapermain-stream manufacturing (e.g., 45 nano-meter to 90 nano-meter) can besufficient for analog and mixed-signal processors to perform AI & MLoperations at lower power consumptions with substantially lower costs.

An objective of the present disclosure is to provide data-convertersthat can be integrated with and seamlessly interface with standarddigital logic (e.g., sea of gates), including for hybrid AI & ML signalprocessing (e.g., main digital signal processors combined with analogmixed-signal accelerators and or co-processors).

Another objective of the present disclosure is to provide current-modedata-converters, multipliers, and multiply-accumulate circuits that caninterface with digital systems and that can perform some of the signalprocessing functions in analog and or mixed-signal for AI & MLapplications, and at low power consumption and cost effectively. Suchcurrent-mode data-converters, multipliers, and multiply-accumulatecircuits can also be used in conjunction with fully-digital systems tofacilitate hybrid mixed-signal, analog, and digital signal processing(or as acceleration IC engines) for AI & ML applications.

Another objective of the present disclosure is to perform some of thesignal condition functions of AI & ML asynchronously by utilizingclock-free data-converters, multipliers, and multiply-accumulatecircuits, which frees signal processing and computations from clockrelated cycle-time delay, dynamic power consumption, and noise relatedto free running clocks.

Substantial amount of current consumption in ML & AI computation (basedon conventional digital processors) is consumed during memory read-writecycle of conventional digital signal processing. Another objective ofthis disclosure is to facilitate mixed-mode signal processing for ML &AI that is memory free and thus reduces power consumption.

Conventional AI & ML digital signal processing rely on centralprocessors on the cloud which increases the overall application powerconsumption due in part to the back-and-forth communications with thecloud-based digital processors. This introduces computation latency thatmay be unacceptable in some applications such as medical. Anotherobjective of this disclosure is to facilitate low power and low costmixed-mode signal processing for ML & AI that can be performed at theedge or on sensors to help eliminate the latency.

Generally, performing AI & ML signal processing on the cloud has privacyrisks.

Another objective of the present disclosure is to enable low power andlow-cost AI & ML analog and mixed signal processing at the edge or onthe sensors to avoid sending and receiving information to and from thecloud.

Another objective of the present disclosure is to provide AI & ML signalprocessing and computation platforms, with current-mode data-converters,multipliers, and multiply-accumulate circuits that can be manufacturedin main-stream Complementary-Metal-Oxide-Semiconductor (CMOS)fabrication which is not only low cost, rugged, and proven but also thatis compatible with digital systems, which facilitates ease of interfacewith existing digital hardware and software platforms.

Another objective of this disclosure is to provide AI & ML signalprocessing and computation platforms utilizing current-modedata-converters, multipliers, and multiply-accumulate circuits that canoperate with low voltage power supplies suitable for portable andbattery-operated AI& ML applications.

Another objective of this disclosure is to provide AI & ML signalprocessing and computation in current-mode, which is inherently fast (inpart) because voltage swings are kept to a minimal in current-modesignal processing. Moreover, current-mode signal processing enablescurrent-mode data-converters, multipliers, and multiply-accumulatecircuits to operate with low voltage power supplies suitable for someportable and battery-operated AI& ML applications.

Another objective of the disclosed invention is to provide AI & MLsignal processing and computation platforms, utilizing analog andmixed-signal solutions whose input signal zero-scale to full-scaledynamic ranges are not limited to high levels or low levels of current.For example, some analog signal processing units may rely on operatingtransistors in the subthreshold regions which restricts the input and oroutput dynamic range of analog signal processing circuits to low currentsignals. Also, some other analog signal processing units may rely onoperating transistors with high currents in the saturation regions whichrestricts the input and or output dynamic range of analog signalprocessing circuits to higher current signals.

Another objective of the disclosed invention is to provide small sizecurrent-mode data-converters, multipliers, and multiply-accumulatecircuits for AI & ML applications that require plurality of suchcircuits to occupy small areas and can be manufactured at low cost.

Another objective of the present disclosure is to providedata-converters that can be arranged with minimal digital circuitry(i.e., be digital-light), thereby saving on die size and reducingdynamic power consumption.

Another objective of the disclosed invention is to provide low glitchand low dynamic power consuming current-mode data-converters,multipliers, and multiply-accumulate circuits utilized in mixed-modemultipliers for AI & ML applications, which accordingly reduce theglitch and dynamic power consumption of for signal processing in AI & MLend-applications.

Another objective of the disclosed invention is to perform analog signalprocessing in current-mode wherein functions such as addition orsubtraction can take small area (e.g., addition of two current signalsrequires just the coupling of two signals), in addition to beinginherently fast.

Another objective of the disclosed invention is to perform analog signalprocessing without using any resistors or capacitors, which reducesmanufacturing size and cost for signal processing in AI & MLend-applications.

Another objective of the disclosed invention is to achieve higheraccuracy multiplication results while utilizing lower resolutionscurrent-mode data converters (which are utilized in the mixed-signalmultipliers). For example, for AI & ML end-applications that requireplurality of such multipliers, it is advantageous to attain higheraccuracy multiplication results by utilizing low resolution iDACs thatoccupy small areas but still achieve higher accuracy multiply-accumulateperformance at lower costs.

Another objective of the disclosed invention is to provide current-modedata-converters, multipliers, and multiply-accumulate circuits which aresymmetric, matched, and scaled. Such arrangement facilitates deviceparameters to track each other over process, temperature, and operatingcondition variations. Accordingly, temperature coefficient, power supplycoefficient, and AC power supply rejection performance of multipliers(that utilize such data converters) for AI & ML applications can beenhanced.

Another objective of the disclosed invention is to provide current-modeanalog and mixed-signal signal processing (utilizing data-converters,multipliers, and multiply-accumulate circuits) that can be asynchronous,consumes low power, have small die size, and provide approximatecomputation as a function of input frequency, for example. Analog andmixed-signal processing may experience errors that can result inapproximate computation but avoid total failures, which can provide theend-application with approximate results to work with instead ofexperiencing failed results in most (all) digital based computations.

Another objective of the disclosed invention is to take advantage ofattenuated contribution of component's random errors in a summationnode. Summing current outputs of a plurality of iDACs would attenuatethe statistical contribution of the cumulative iDAC's random errors(such as random noise, offset, mismatches, linearity, gain, drift, etc.)at the summing node where the iDAC's current outputs are coupled. Thestatistical contribution of such cumulative iDAC's random errors, at thesumming node, is the square root of the sum of the squares of suchrandom error terms.

Another objective of the disclosed invention is to provide analog andmixed signal processors for AI & ML that neither require very expensivenor bleeding-edge deep sub-micron (e.g., 10 nano-meter geometries)manufacturing. Generally, purely digital AI & ML systems can achievehigh-speed and high-density relying chiefly on very expensivebleeding-edge deep sub-micron manufacturing (whose transistors are fastand dense) whose costs may be prohibitive in non-cloud high-volume AI &ML applications near the edge or on sensors with intelligence. Moreover,signal processors on the edge or on sensors may not need very highcomputation speeds given their more dedicated and smaller AI & MLrelated tasks, in part because such processors may not need to be sharedor multi-tasked on edge devices or sensors. Therefore, utilizing analogand mixed signal processing for AI & ML on edge devices and sensors,which can perform to specifications by using inexpensive main-streammanufacturing, avoids the unnecessary (fast and dense) and veryexpensive bleeding-edge deep sub-micron manufacturing that is generallyrequired by digital AI & ML processors.

Another objective of the disclosed invention is to provide plurality of(data-converters, multipliers, and multiply-accumulate circuits toperform) analog and mixed signal processors for AI & ML application,wherein the analog and mixed signal processors can be made small, buttheir precision can be enhanced via a shared centrally calibrated (ortrimmed) network.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram illustrating a floatingcurrent-mode (i) digital-to-analog-converter (iDAC) method.

FIG. 2 is a simplified circuit schematic diagram illustrating anembodiment of an iDAC that utilizes the floating iDAC method illustratedin FIG. 1.

FIG. 3 is a simplified circuit schematic diagram illustrating anembodiment of an iDAC that combines a plurality of iDACs in order toarrange a higher resolution iDAC, wherein at least one of the pluralityof iDACs utilizes the floating iDAC method illustrated in FIG. 1.

FIG. 4 is a simplified circuit schematic diagram illustrating anotherembodiment of an iDAC that combines a plurality of iDACs in order toarrange a higher resolution iDAC, wherein at least one of the pluralityof iDACs utilizes the floating iDAC method illustrated in FIG. 1.

FIG. 5 is a simplified schematic diagram illustrating a mixed-signalcurrent-mode digital-input to analog-current-output multiplier(XD_(i)I_(o)) comprising of a first iDAC whose output is coupled to thereference input of a second iDAC, wherein the first and second iDACsutilize the floating iDAC method illustrated in FIG. 1.

FIG. 6 is a simplified circuit schematic diagram illustrating anotherembodiment of an iDAC that utilizes the floating iDAC method illustratedin FIG. 1.

FIG. 7 is a simplified functional block diagram illustrating afactorized iDAC method.

FIG. 8 is a simplified circuit schematic diagram illustrating anembodiment of an iDAC that utilizes the factorized iDAC methodillustrated in FIG. 7.

FIG. 9 is a simplified circuit schematic diagram illustrating anotherembodiment of an iDAC that combines the factorized and floating DACmethods illustrated FIG. 7 and FIG. 1, respectively.

FIG. 10 is a simplified circuit schematic diagram illustrating anotherembodiment of another iDAC that utilizes the factorized and floating DACmethods illustrated FIG. 7, and FIG. 1, respectively.

FIG. 11 is a simplified circuit schematic diagram illustrating anembodiment of a mixed-signal current-mode digital-input to analog-outputmultiplier (XD_(i)I_(o)) comprising of a first iDAC whose output iscoupled to the reference input of a second iDACs, wherein the first andsecond iDACs utilize the factorized and floating DAC methods illustratedFIG. 7, and FIG. 1, respectively.

FIG. 12, including FIG. 12A and FIG. 12B, is a (Simulation Program withIntegrated Circuits Emphasis) SPICE circuit simulation showing thelinearity waveforms of the mixed-signal current-mode digital-input toanalog-current-output multiplier (XD_(i)I_(o)) that is illustrated inFIG. 11.

FIG. 13 is a simplified circuit schematic diagram illustrating anembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is a mixed-signalcurrent-mode digital-input to analog-current-output (D_(i)I_(o)) scalarmultiply-accumulate (sMAC) circuit utilizing current-modedigital-to-analog-converters (iDAC).

FIG. 14 is a simplified functional block diagram illustrating anotherembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signalcurrent-mode digital-input to analog-current-output (D_(i)I_(o)) scalarmultiply-accumulate (sMAC) circuit utilizing current-modedigital-to-analog-converters (iDAC).

FIG. 15 is a simplified functional block diagram illustrating anotherembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signalcurrent-mode digital-input to digital-output (D_(i)D_(o)) scalarmultiply-accumulate (sMAC) plus bias circuit utilizing current-modedigital-to-analog-converters (iDAC) and current-mode analog-to-digitalconverters (iADC).

FIG. 16 is a simplified functional block diagram illustrating anotherembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signalcurrent-mode digital-input to digital-output (D_(i)D_(o)) scalarmultiply-accumulate (sMAC) plus bias circuit utilizing current-modedigital-to-analog-converters (iDAC) and current-mode analog-to-digitalconverters (iADC).

FIG. 17 is a simplified functional block diagram illustrating anembodiment of a mixed-signal current-mode multiply-accumulate (iMACiDAC)circuit. The disclosed iMACiDAC is a mixed-signal current-modedigital-input to digital-output (D_(i)D_(o)) multiply-accumulate (iMAC)circuit plus bias circuit utilizing current-modedigital-to-analog-converters (iDAC) and current-mode analog-to-digitalconverters (iADC).

FIG. 18 is a simplified functional block diagram illustrating anembodiment of a mixed-signal current-mode Artificial Neural Network(iANN) circuit. The disclosed iANN is a mixed-signal current-modedigital-input to digital-output (D_(i)D_(o)) iANN circuit utilizingcurrent-mode multiply-accumulate (iMAC) circuits that utilizecurrent-mode digital-to-analog-converter (iDAC) and current-modeanalog-to-digital converter (iADC) circuits.

FIG. 19 is a simplified circuit schematic diagram illustrating anembodiment of a multi-channel mixed-signal current-modedigital-to-analog converter (iDAC) utilizing the multiple-channeldata-converter method, wherein a central reference bias network (RBN)shares its reference bias voltage bus with plurality of currentreference networks of respective plurality of data-converters.

FIG. 20 is a simplified circuit schematic illustrating an embodiment fora plurality-channels of mixed-mode multiplier (XD_(i)I_(o)) withdigital-input to analog-current-output that is multi-quadrant, whereinthe XD_(i)I_(o) utilizes the multiple-channel data-converter methoddisclosed in section 19.

FIG. 21 is a simplified circuit schematic illustrating an embodiment fora plurality-channels multiplier (XD_(i)I_(o)) with digital-input toanalog-current-output that is single-quadrant, wherein the XD_(i)I_(o)utilizes the multiple-channel data-converter method disclosed in section19, and wherein the XD_(i)I_(o) utilizes a power supply desensitization(PSR) method.

FIG. 22A is a circuit simulation illustrating the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to anoutput current (I_(o)) of a current-output DAC (iDAC). Here, themultiple-channel data-converter method of section 19 is utilized wherethe reference bias network (RBN) is not trimmed, and the iDAC isarranged similar to that of FIG. 19 but having an 8-bit resolution.

FIG. 22B is a circuit simulation illustrating the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to anoutput current (I_(o)) of a current-output DAC (iDAC). Here, themultiple-channel data-converter method of section 19 is utilized wheretwo Most-Significant-Bits (MSBs) of the reference bias network (RBN) aretrimmed, and the iDAC is arranged similar to that of FIG. 19 but havingan 8-bit resolution.

FIG. 23 is a simplified circuit schematic illustrating an embodiment ofa multiplier (XD_(i)I_(o)) with digital-inputs to analog-current-outputthat operate in current mode comprising of a first current-output DAC(iDAC) or iDACx₂₃ whose analog-current-output supplies the referenceinput to a second current-output iDAC or iDACy₂₃.

FIG. 24 is a simplified circuit schematic illustrating anotherembodiment of a multiplier (XD_(i)I_(o)) with digital-inputs toanalog-current-output that operate in current mode comprising of a firstcurrent-output DAC (iDAC) or iDACx₂₄ whose analog-current-outputsupplies the reference input to a second current-output iDAC or iDACy₂₄.

FIG. 25 is a simplified circuit schematic illustrating an embodiment ofa multiplier (XD_(i)I_(o)) with digital-input to analog-current-outputthat operate in current mode equipped with an embodiment of the powersupply desensitization (PSR) circuit.

FIG. 26 is a simplified circuit schematic illustrating anotherembodiment of a multiplier (XD_(i)I_(o)) with digital-input toanalog-current-output that operate in current mode equipped with anotherembodiment of the power supply desensitization (PSR) circuit.

FIG. 27 is a simplified circuit schematic illustrating anotherembodiment of a multiplier (XD_(i)I_(o)) with digital-input toanalog-current-output that operate in current mode comprising of a firstcurrent-output DAC (iDAC) or iDACx₂₇ whose analog-current-outputsupplies the reference input to a second current-output iDAC or iDACy₂₇.

FIG. 28 is a circuit simulations illustrating the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to anoutput current (I_(o)) of a XD_(i)I_(o) multiplier arranged similar tothat of FIG. 21 but having an 8-bit digital inputs instead of 3-bits.

FIG. 29 is a circuit simulations illustrating the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to anoutput current (I_(o)) of a XD_(i)I_(o) multiplier arranged similar tothat of FIG. 20 but having an 8-bit digital inputs instead of 4-bits.

FIG. 30 is a simplified circuit schematic illustrating anotherembodiment for a plurality-channels multiplier (XD_(i)I_(o)) withdigital-input to analog-current-output that is single-quadrant, whereinthe XD_(i)I_(o) multiplier utilizes the multiple-channel data-convertermethod disclosed in section 19 and the XD_(i)I_(o) multiplier utilizes apower supply desensitization (PSR) circuit.

FIG. 31 is a circuit simulations showing the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to theoutput current (I_(o)) of a XD_(i)I_(o) multiplier that is arrangedsimilar to that of FIG. 30 but having an 8-bit digital inputs instead of3-bits.

FIG. 32 is a simplified block diagram illustrating a mesheddigital-to-analog multiplication (mD_(i)S_(o)) method.

FIG. 32′ is another simplified block diagram illustrating the mesheddigital-to-analog multiplication (mD_(i)S_(o)) method that is disclosedin section 32.

FIG. 33 is a simplified circuit schematic illustrating an embodiment ofa digital-input to analog current output multiplier (XD_(i)I_(o)) thatutilizes the meshed digital-to-analog multiplication (mD_(i)S_(o))method described in the prior section 32′.

FIG. 34 is a simplified circuit schematic illustrating anotherembodiment of a digital-input to analog current output multiplier(XD_(i)I_(o)) that utilizes the meshed digital-to-analog multiplication(mD_(i)S_(o)) method described in section 32 and section 32′.

FIG. 35 is a simplified circuit schematic illustrating anotherembodiment of a digital-input to analog current output multiplier(XD_(i)I_(o)) that utilizes the meshed digital-to-analog multiplication(mD_(i)S_(o)) method described in section 32.

FIG. 36 is a simplified block diagram illustrating a first non-lineardigital-to-analog converter (NDAC) method.

FIG. 36′ is a simplified block diagram illustrating a second non-lineardigital-to-analog converter (NDAC) method, which utilizes the mesheddigital-to-analog multiplication (mD_(i)S_(o)) method that is discussedin section 32.

FIG. 37 is a simplified block diagram illustrating a third non-lineardigital-to-analog converter (NDAC) method.

FIG. 38 is a simplified circuit schematic illustrating an embodiment ofa non-linear digital-input to analog current output digital-to-analogconverter (iNDAC₃₈), which utilizes the NDAC method described in section37, wherein the non-linear output profile of iNDAC₃₈ is programmed toapproximate a square transfer function.

FIG. 39 is a simplified circuit schematic illustrating anotherembodiment of a non-linear digital-input to analog current outputdigital-to-analog converter (iNDAC₃₉), which utilizes the NDAC methoddescribed in section 36′ wherein the non-linear output profile ofiNDAC₃₉ is programmed to approximate a square transfer function.

FIG. 40 is a simplified circuit schematic illustrating anotherembodiment of the digital-input to analog current output multiplier(XD_(i)I_(o)) that utilizes the meshed digital-to-analog multiplication(mD_(i)S_(o)) method described in the prior section 32, and wherein theXD_(i)I_(o) multiplier utilizes the multiple-channel data-convertermethod disclosed in section 19 when plurality of XD_(i)I_(o) multipliersare needed by an end-application.

FIG. 41 is a simplified circuit schematic illustrating anotherembodiment of the digital-input to analog current output multiplier(XD_(i)I_(o)), which can be extended to plurality of XD_(i)I_(o)multipliers by sharing a central reference bias network (RBN) that biasthe current reference network of each of the XD_(i)I_(o) multipliers.

FIG. 42 is a SPICE circuit simulations that illustrates the linearityerror in % between an ideal output current (Io_(ideal)) of a XD_(i)I_(o)multiplier versus the simulated output current (Io_(simulation)) of aXD_(i)I_(o) multiplier that is arranged similar to that of FIG. 34 buthaving a 4-bit resolution.

FIG. 43 is a SPICE circuit simulations that illustrates the linearityerror in % between an ideal output current (Io_(ideal)) of a XD_(i)I_(o)multiplier versus the simulated output current (Io_(simulation)) of aXD_(i)I_(o) multiplier that is arranged similar to that of FIG. 40 butwith a 6-bit resolution.

FIG. 44 illustrates a SPICE circuit simulations comprising of an idealsquare iDAC's output current (I_(X) ²) plot versus the simulated outputcurrent (I_(O) ²) plot of a square iDAC that is arranged similar to thatof FIG. 38 but with a 7-bit resolution.

FIG. 45 illustrates SPICE circuit simulations comprising of an idealsquare iDAC's output current (I_(X) ²) plot versus the simulated outputcurrent (I_(O) ²) plot of a square iDAC that is arranged similar to thatof FIG. 39 but with a 7-bit resolution.

FIG. 46 illustrates SPICE circuit simulations comprising of an idealXD_(i)I_(o) multiplier's output current (Io_(ideal)) plot versus thesimulated output current (Io_(simulation)) plot of a XD_(i)I_(o)multiplier that is arranged similar to that of FIG. 41 but with a 7-bitresolution.

SUMMARY OF THE DISCLOSURE

An aspect of the present disclosure is a floating current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefloating iDAC method comprising: programming a plurality ofvoltage-controlled-current sources (VCCS) to generate a plurality ofcurrent signals to be at least one of equally weighted currents,binarily weighted currents, non-linear weighted currents, andindividually weighted currents; summing the plurality of current signalsto create a summation current signal (S_(SUM)) at a reference currentinput port (A_(R)); wherein the floating iDAC has a digital input word(D_(i)) that controls a plurality of current switches (iSW) thatrespectively steer the plurality of current signals to at least one of apositive current output port (I_(O) ⁺), and a negative current outputport (I_(O) ⁻) of the floating iDAC; wherein the currents flowingthrough the I_(O) ⁺ port and the I_(O) ⁻ port are proportional to thecurrent signal flowing through the A_(R) port, and responsive to theD_(i) word of the floating iDAC. Further aspects of the floatingcurrent-mode digital-to-analog converter (iDAC) method in an integratedcircuit, the floating iDAC method further comprising: receiving currentsignals from respective I_(O) ⁺ ports and I_(O) ⁻ ports, of at least oneof a subsequent iDAC, into the respective at least one of the I_(O) ⁺port, and the I_(O) ⁻ port of the floating iDAC; wherein the A_(R) portreceives a reference current signal (S_(R)); wherein the reference inputsignal of each of the subsequent iDACs is proportional to the S_(R)signal; and wherein the at least one of the subsequent iDACs effectivelyincreases the resolution of the floating iDAC. Further aspects of thefloating current-mode digital-to-analog converter (iDAC) method in anintegrated circuit, the floating iDAC method further comprising:receiving the current signal from a first iDAC into a reference inputport of a second iDAC, wherein at least one of the first iDAC and thesecond iDAC is the floating iDAC; generating a multiplicand outputcurrent signal (S_(MULT)) at an output port of the second iDAC; andwherein the S_(MULT) signal is proportional to the S_(R) signal andresponsive to the product of a digital input word of the first iDAC and,a digital input word of the second iDAC. Further aspects of the floatingcurrent-mode digital-to-analog converter (iDAC) method in an integratedcircuit, the floating iDAC method further comprising: generating aplurality of S_(MULT) signals; and combining the plurality of S_(MULT)signals to generate a multiply-accumulate current signal (S_(MAC)),wherein the S_(MAC) signal is a summation of the plurality of theS_(MULT) signals. Further aspects of the floating current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefloating iDAC method further comprising: combining the S_(MAC) signalwith a bias current signal (S_(B)) from a bias current iDAC to generatea biased multiply-accumulate current signal (S_(BMAC)), wherein theS_(BMAC) signal is the summation of the S_(MAC) signal and the S_(B)signal. Further aspects of the floating current-mode digital-to-analogconverter (iDAC) method in an integrated circuit, the floating iDACmethod further comprising: digitizing the S_(BMAC) signal in acurrent-mode analog-to-digital converter (iADC). Further aspects of thefloating current-mode digital-to-analog converter (iDAC) method in anintegrated circuit, the floating iDAC method further comprising:combining a plurality of S_(BMAC) signals, wherein the combining theplurality of S_(BMAC) signals forms a current-mode artificial neuralnetwork (iANN). Further aspects of the floating current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefloating iDAC method further comprising: receiving currents from I_(O) ⁺port and I_(O) ⁻ port, of a plurality of subsequent floating iDACs, intothe respective I_(O) ⁺ port and the I_(O) ⁻ port of the floating iDAC togenerate an I_(Op) ⁺ and an I_(Op) ⁻; generating a plurality ofreference current sources (S_(R))s to be at least one of equallyweighted currents, binarily weighted currents, non-linear weightedcurrents, and individually weighted currents; receiving each of theplurality of S_(R) signals respectively into the I_(SR) port of eachsubsequent floating iDAC; receiving a X digital word of width m, and a Ydigital word of width n, wherein each bit weight of the X word of widthm corresponds to the respective weight of each of the plurality ofreference currents corresponding respectively to each of the floatingiDACs, and wherein each bit weight of the Y word of width n correspondsto the digital input word D_(i) of the plurality of floating iDACs;generating a multiplicand output current signal (S_(MULT)) in at leastone of the I_(Op) ⁺ port and I_(O)p port; wherein the I_(iMULT) currentis proportional to the magnitude of S_(R) source, and responsive to theproduct of the X word and the Y word; and wherein the X word and Y wordare interchangeable.

Another aspect of the present disclosure is a floating current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefloating iDAC method comprising: generating a plurality of currents in aplurality of metal-oxide-semiconductor-field-effect-transistors(MOSFETs), wherein a weighting relationship among each of the pluralityof currents in the MOSFETs is at least one of equally weighted, binarilyweighted, non-linear weighted, and individually weighted; steering eachof the plurality of current signals in the plurality of MOSFETsrespectively through each input terminal of a plurality of currentswitches (iSW); steering each of the plurality of current signalsthrough the plurality of iSWs respectively to each output terminal ofthe plurality of current switches (iSW) to at least one of a positivecurrent output port (I_(O) ⁺), and a negative current output port (I_(O)⁻); receiving a digital input word (D_(i)), and respectively controllingthe steering of each of the plurality of current signals through theplurality of iSWs by the D_(i); wherein respective source ports of theplurality of MOSFETs are coupled together, and coupled to a referencecurrent source (S_(R)); wherein respective gate terminals of theplurality of MOSFETs are coupled together, and coupled to a voltagesource (V_(B)); and wherein the currents flowing through the I_(O) ⁺port and the I_(O) ⁻ port are proportional to the magnitude of the S_(R)source, and responsive to the D_(i) word of a floating iDAC. Furtheraspects of the floating current-mode digital-to-analog converter (iDAC)method in an integrated circuit, the floating iDAC method furthercomprising: receiving into the at least one of the I_(O) ⁺ port, and theI_(O) ⁻ port of the floating iDAC, currents from respective I_(O) ⁺ports and I_(O) ⁻ ports from at least one of a subsequent iDAC, whereinthe at least one of the subsequent iDAC effectively increases theresolution of the floating iDAC. Further aspects of the floatingcurrent-mode digital-to-analog converter (iDAC) method in an integratedcircuit, the floating iDAC method further comprising: receiving theoutput current signal from a first iDAC into a reference input port of asecond iDAC, wherein at least one of the first iDAC and the second iDACis the floating iDAC; and generating a multiplicand output currentsignal (S_(MULT)) at an output of the second iDAC. Further aspects ofthe floating current-mode digital-to-analog converter (iDAC) method inan integrated circuit, the floating iDAC method further comprising:generating a plurality of S_(MULT) signals; and combining the pluralityof S_(MULT) signals to generate a multiply-accumulate current signal(S_(MAC)), wherein the S_(MAC) signal is a summation of the plurality ofthe S_(MULT) signals. Further aspects of the floating current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefloating iDAC method further comprising: generating a bias currentsignal (S_(B)) by an iDAC; and combining the S_(MAC) signal with theS_(B) signal to generate a biased multiply-accumulate current signal(S_(BMAC)), wherein the S_(BMAC) signal is a summation of the S_(MAC)signal and the S_(B) signal. Further aspects of the floatingcurrent-mode digital-to-analog converter (iDAC) method in an integratedcircuit, the floating iDAC method further comprising: digitizing theS_(BMAC) signal in a current-mode analog-to-digital converter (iADC).Further aspects of the floating current-mode digital-to-analog converter(iDAC) method in an integrated circuit, the floating iDAC method furthercomprising: combining a plurality of S_(BMAC) signals, wherein thecombining the plurality of S_(BMAC) signals forms a current-modeartificial neural network (iANN).

Another aspect of the present disclosure is a mixed-signal current-modemultiply-accumulate (iMAC) method in integrated circuits, themixed-signal iMAC method comprising: generating a plurality of firstcurrent output signals (S1 _(o))s by a plurality of first current-modedigital-to-analog converters (iDAC1)s; receiving the plurality of S1_(o) signals into a respective plurality of reference input ports (A2_(R)) of a plurality of second current-mode digital-to-analog-converters(iDAC2)s; generating a plurality of multiplicand output current signals(S_(MULT))s at the plurality of A2 _(R) ports; combining a plurality ofS_(MULT) signals together to generate a multiply-accumulate currentsignal (S_(MAC)); and wherein the S_(MAC) signal is a summation of aplurality of second current output signals (S2 _(o))s of the pluralityof iDAC2 s. Further aspects of the mixed-signal current-modemultiply-accumulate (iMAC) method in integrated circuits, themixed-signal iMAC method further comprising: generating a bias currentsignal (S_(B)) by a bias iDAC; and combining the S_(MAC) signal with theS_(B) signal to generate a biased multiply-accumulate current signal(S_(BMAC)), wherein the S_(BMAC) signal is a summation of the S_(MAC)signal and the S_(B) signal. Further aspects of the mixed-signalcurrent-mode multiply-accumulate (iMAC) method in integrated circuits,the mixed-signal iMAC method further comprising: digitizing the S_(BMAC)signal in a current-mode analog-to-digital converter (iADC). Furtheraspects of the mixed-signal current-mode multiply-accumulate (iMAC)method in integrated circuits, the mixed-signal iMAC method furthercomprising: combining a plurality of S_(BMAC) signals, wherein thecombining the plurality of S_(BMAC) signals forms a current-modeartificial neural network (iANN).

Another aspect of the present disclosure is a factorized current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefactorized iDAC method comprising: generating a scaled top outputcurrent signal (A_(t) F_(t)) as a product of a top scale factor (F_(t))and a top output current signal (A_(t)) of a top iDAC (iDAC_(t)),wherein the iDAC_(t) receives a top digital word (D_(t)) that is t-bitswide, and wherein the iDAC_(t) receives a top reference current signal(t_(R)), and wherein the iDAC_(t) is binary weighted and wherein F_(t)and t are each between zero and eight; generating a scaled middle outputcurrent signal (A_(m) F_(m)) as a product of a middle scale factor(F_(m)) and a middle output current signal (A_(m)) of a middle iDAC(iDAC_(t)), wherein the iDAC_(m) receives a middle digital word (D_(m))that is m-bits wide, and wherein the iDAC_(m) receives a middlereference current signal (m_(R)), and wherein iDAC_(m) is binaryweighted and wherein the F_(m) and m are each between zero and eight;combining the A_(t)F_(t), and the A_(m)F_(m) signals to generate asummation analog output current signal (A_(Otm)) of a factorized iDAC;wherein a digital input word (D_(i)) of the factorized iDAC is t+m bitswide, and wherein the D_(t) is the most-significant-bits bank of theD_(i), and wherein the D_(m) is a remaining-bits bank of the D_(i), andwherein the factorized iDAC_(t) is binary weighted; and whereinA_(Otm)=A_(t)F_(t)+F_(m) wherein (F_(t)/F_(m))×(m_(R)/t_(R))=2^(t); andwherein the t_(R), and m_(R) signals are proportional to one another andproportional to a reference input signal (S_(R)) of the factorized iDAC.

Another aspect of the present disclosure is a factorized current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefactorized iDAC method comprising: generating a scaled top outputcurrent signal (A_(t)F_(t)) as a product of a top scale factor (F_(t))and a top output current signal (A_(t)) of a top iDAC (iDAC_(t)),wherein the iDAC_(t) receives a top digital word (D_(t)) that is t-bitswide, and wherein the iDAC_(t) receives a top reference current signal(t_(R)), and wherein iDAC_(t) is binary weighted, and wherein F_(t) andt are each between zero and eight; generating a scaled middle outputcurrent signal (A_(m) F_(m)) as a product of a middle scale factor(F_(m)) and a middle output current signal (A_(m)) of a middle iDAC(iDAC_(t)), wherein the iDAC_(m) receives a middle digital word (D_(m))that is m-bits wide, and wherein the iDAC_(m) receives a middlereference current signal (m_(R)), and wherein iDAC_(m) is binaryweighted, and wherein the F_(m) and m are each between zero and eight;generating a scaled bottom output current signal (A_(b)F_(b)) by scalinga bottom binary iDAC (DAC_(b)) output current signal (A_(b)) by a bottomscale factor F_(b), wherein the iDAC_(b) receives a bottom digital word(D_(b)) that is b-bits wide, and wherein the iDAC_(b) receives a bottomreference current signal (b_(R)), and wherein the F_(b) and b are eachintegers greater than one and less than eight; combining the A_(t)F_(t),the A_(m)F_(m), and the A_(b)F_(b) signals to generate a summationanalog output current signal (A_(Otm)) of a factorized iDAC; whereinA_(Otm)=A_(t)F_(t)+A_(m)F_(m)+A_(b)F_(b); wherein(F_(t)/F_(b))×(b_(R)/t_(R))=2^(t+m); wherein the digital input (D_(i))of the factorized iDAC is t+m+b bits wide, and wherein the D_(t) is themost-significant-bits (MSBs) bank of the D_(i), and wherein the D_(m) isthe intermediate-bits (ISBs) bank of the D_(i), and wherein the D_(b) isthe least-significant-bits (LSBs) bank of the D_(i); and wherein thet_(R), m_(R), and b_(R) signals are proportional to one another andproportional to a reference input signal (S_(R)) of the factorized iDAC.Further aspects of the factorized current-mode digital-to-analogconverter (iDAC) method in an integrated circuit, the factorized iDACmethod further comprising: receiving the output current signal from afirst iDAC into a reference input port of a second iDAC, wherein atleast one of the first iDAC and the second iDAC is the factorized iDAC;generating a multiplicand output current signal (S_(MULT)) at an outputport of the second iDAC; and wherein the S_(MULT) signal is proportionalto the S_(R) signal and responsive to the product of digital input wordsof the first iDAC and the second iDAC. Further aspects of the factorizedcurrent-mode digital-to-analog converter (iDAC) method in an integratedcircuit, the factorized iDAC method further comprising: generating aplurality of S_(MULT) signals; and combining the plurality of S_(MULT)signals to generate a multiply-accumulate current signal (S_(MAC)),wherein the S_(MAC) signal is a summation of the plurality of theS_(MULT) signals. Further aspects of the factorized current-modedigital-to-analog converter (iDAC) method in an integrated circuit, thefactorized iDAC method further comprising: generating a bias currentsignal (S_(B)) by a bias iDAC; and combining the S_(MAC) signal with theS_(B) signal to generate a biased multiply-accumulate current signal(S_(BMAC)), wherein the S_(BMAC) signal is a summation of the S_(MAC)signal and the S_(B) signal. Further aspects of the factorizedcurrent-mode digital-to-analog converter (iDAC) method in an integratedcircuit, the factorized iDAC method further comprising: digitizing theS_(BMAC) signal in a current-mode analog-to-digital converter (iADC).Further aspects of the factorized current-mode digital-to-analogconverter (iDAC) method in an integrated circuit, the factorized iDACmethod further comprising: combining a plurality of S_(BMAC) signals,wherein the combining the plurality of S_(BMAC) signals forms acurrent-mode artificial neural network (iANN).

Another aspect of the present disclosure is a mixed-signal scalarcurrent-mode multiply-accumulate (iMAC) method in an integrated circuit,the mixed-signal scalar iMAC method comprising: generating a scalarcurrent (S_(S)) by a first current-mode DAC (iDAC); replicating theS_(S) signal to generate a plurality of scalar current replica signals(S_(SD)); receiving the plurality of S_(SD) signals respectively into areference input of each of a plurality of second iDACs; and generating aplurality of current output Signals (S_(o))s of the plurality of thesecond iDACs; combining the plurality of S_(o) signals of the pluralityof second iDACs to generate a multiply-accumulate current (S_(MAC)); andwherein the S_(MAC) is a summation of the respective plurality of S_(o)signals. Further aspects of the mixed-signal scalar current-modemultiply-accumulate (iMAC) method in an integrated circuit, themixed-signal scalar iMAC method further comprising: combining theS_(MAC) signal with a bias current signal (S_(B)) from a bias currentiDAC to generate a biased multiply-accumulate current signal (S_(BMAC)),wherein the S_(BMAC) signal is the summation of the S_(MAC) signal andthe S_(B) signal. Further aspects of the mixed-signal scalarcurrent-mode multiply-accumulate (iMAC) method in an integrated circuit,the mixed-signal scalar iMAC method further comprising: digitizing theS_(BMAC) signal in a current-mode analog-to-digital converter (iADC).Further aspects of the mixed-signal scalar current-modemultiply-accumulate (iMAC) method in an integrated circuit, themixed-signal scalar iMAC method further comprising: combining aplurality of S_(BMAC) signals, wherein the combining the plurality ofS_(BMAC) signals forms a current-mode artificial neural network (iANN).

Another aspect of the present disclosure is a mixed-signal scalarcurrent-mode multiply-accumulate (iMAC) method in an integrated circuit,the mixed-signal scalar iMAC method comprising: receiving a first andsubsequent reference current signals, each respectively to a referenceport (A_(R)) of each of first current mode iDAC of a plurality of firstcurrent mode iDACs; generating a plurality of output current signals(S_(o))s by the plurality of first current-mode DACs (iDAC); combiningthe plurality of S_(O) signals of the plurality of first iDACs togenerate a current signal (S_(Osum)), wherein the S_(Osum) is asummation of the plurality of S_(O) signals; mirroring the S_(Osum)signal to create a mirrored S_(Osum) signal, S_(Osumm); receiving theS_(Osumm) signal into a reference input port of a scalar iDAC; andgenerating a multiply-accumulate current signal (S_(MAC)) at the outputport of the scalar iDAC. Further aspects of the mixed-signal scalarcurrent-mode multiply-accumulate (iMAC) method in integrated circuits,the mixed-signal scalar iMAC method further comprising: combining theS_(MAC) signal with a bias current signal (S_(B)) from a bias currentiDAC to generate a biased multiply-accumulate current signal (S_(BMAC)),wherein the S_(BMAC) signal is the summation of the S_(MAC) signal andthe S_(B) signal. Further aspects of the mixed-signal scalarcurrent-mode multiply-accumulate (iMAC) method in an integrated circuit,the mixed-signal scalar iMAC method further comprising: digitizing theS_(BMAC) signal in a current-mode analog-to-digital converter (iADC).Further aspects of the mixed-signal scalar current-modemultiply-accumulate (iMAC) method in an integrated circuit, themixed-signal scalar iMAC method further comprising: combining aplurality of S_(BMAC) signals, wherein the combining the plurality ofS_(BMAC) signals forms a current-mode artificial neural network (iANN).

Another aspect of the present disclosure is a non-lineardigital-to-analog conversion (NDAC) method in an integrated circuit, themethod comprising: generating a non-linear Most-Significant-Portion(MSP) analog output signal (So_(MPS) ^(N)) that is proportional to a MSPreference signal (Sr_(MSP)), and is responsive to a bank ofMost-Significant-Bits (MSBs) of a digital input word (Di_(MSP));generating a linear Least-Significant-Portion (LSP) analog output signal(So_(LSP) ^(L)) that is proportional to a LSP reference signal(Sr_(LSP)), and is responsive to a bank of Least-Significant-Bits (LSBs)of a digital word (Di_(LSP)), and is responsive to the Di_(MSP) word;combining the So_(MPS) ^(N) signal and the So_(LSP) ^(L) signal togenerate a non-linear analog output signal (So_(N)) that is proportionalto a reference signal (S_(R)), and is responsive to a digital word(D_(I)); wherein the So_(LSP) ^(L) signal is a straight-lineapproximation between non-linear segments of the So_(MPS) ^(N) signal;wherein the Sr_(MSP) signal, and the Sr_(LSP) signal, are eachproportional to the S_(R) signal; and wherein the D_(I) word iscomprised of the Di_(MSP) word and the Di_(LSP) word. Further aspects ofthe non-linear digital-to-analog conversion (NDAC) method in anintegrated circuit, the method further comprising: wherein the So_(MPS)^(N) signal is generated by a non-linear MSP digital-to-analog converter(DAC_(MSP) ^(N)) having a reference network comprised of a sequence ofscaled MSP reference signals (Sr_(MSP) ^(N)); and wherein the sequenceof scaled Sr_(MSP) ^(N) signals are at least one of squarely weighted,logarithmically weighted, non-linearly weighted, and individuallyweighted. Further aspects of the non-linear digital-to-analog conversion(NDAC) method in an integrated circuit, the method further comprising:generating the So_(LSP) ^(L) signal by a plurality of linear LSPDigital-to-Analog Converters (DAC_(LSP) ^(L))s comprised of a firstlinear LSP DAC (DAC1 _(LSP) ^(L)), and a second linear LSP DAC (DAC2_(LSP) ^(L)); generating an output signal (So1 _(LSP) ^(L)) by the DAC1_(LSP) ^(L) that is proportional to a first LSP reference signal (Sr1_(LSP)), and is responsive to the Di_(MSP) word; combining the So1_(LSP) ^(L) signal with a reference offset signal (Sr1 _(LSP)) togenerate a second reference signal (Sr2 _(LSP) ^(L)); receiving the Sr2_(LSP) ^(L) signal into a reference input port (Ar2 _(LSP) ^(L)) of theDAC2 _(LSP) ^(L); and generating the So_(LSP) ^(L) signal at an outputport (Ao2 _(LSP) ^(L)) of the DAC2 _(LSP) ^(L) that is responsive to theDi_(LSP) word and the Di_(MSP) word. Further aspects of the non-lineardigital-to-analog conversion (NDAC) method in an integrated circuit, themethod further comprising: multiplying the Di_(LSP) word and theDi_(MSP) word to generate a multiplicand digital word(Di_(LSP)×Di_(MSP)); generating an output signal (So1 _(LSP) ^(L)) by afirst LSP Digital-to-Analog Converter (DAC1 _(LSP) ^(L)), wherein theSo1 _(LSP) ^(L) signal is proportional to a first LSP reference signal(Sr1 _(LSP)), and is responsive to the Di_(LSP)×Di_(MSP) word;generating an output offset signal (Sfo_(LSP) ^(L)) by a second LSPDigital-to-Analog-Converter (DAC2 _(LSP) ^(L)), wherein Sfo_(LSP) ^(L)signal is proportional to a second LSP reference signal (Sr2 _(LSP)),and is responsive to the Di_(LSP) word; and combining the So1 _(LSP)signal and the Sfo_(LSP) ^(L) signal to generate the So_(LSP) ^(L)signal. Further aspects of the non-linear digital-to-analog conversion(NDAC) method in an integrated circuit, the method further comprising:receiving the Di_(LSP) word and the Di_(MSP) word into a linearly mesheddigital-input to analog-output multiplier (mDiSo_(LSP) ^(L)) to generatean output signal (So1 _(LSP) ^(L)) that is proportional to a first LSPreference signal (Sr1 _(LSP)); generating an output offset signal(Sfo_(LSP) ^(L)) by a second LSP Digital-to-Analog-Converter (DAC2_(LSP) ^(L)) that is proportional to a second LSP reference signal (Sr2_(LSP)), and is responsive to the Di_(LSP) word; and combining So1_(LSP) ^(L) signal and the Sfo_(LSP) ^(L) signal to generated theSo_(LSP) ^(L) signal. Further aspects of the non-lineardigital-to-analog conversion (NDAC) method in an integrated circuit, themethod further comprising: generating at least one So_(MPS) ^(N) by atleast one non-linear MSP Digital-to-Analog Converter (DAC_(MSP) ^(N));generating at least one So_(LSP) ^(L) by at least one linear LSPDigital-to-Analog Converter (DAC_(LSP) ^(L)); generating at least oneSo_(N) signal that is proportional to the reference signal (S_(R)),wherein the at least one So_(N) signal is responsive to at least oneD_(i) word; wherein the reference network of each of the DAC_(MSP) ^(N)is comprised of a sequence of non-linearly scaled MSP reference signals(Sr_(MSP) ^(N)) that are proportional to the Sr_(MSP) signal; whereinthe reference network of each of the DAC_(LSP) ^(L) is comprised of asequence of scaled LSP reference signals (Sr_(LSP) ^(L)) that areproportional to the Sr_(LSP) signal; wherein each of the sequence ofSr_(MSP) ^(N) signals is at least one of squarely weighted,logarithmically weighted, non-linearly weighted, and individuallyweighted; wherein each of the sequence of Sr_(LSP) ^(L) signals is atleast one of binary weighted, linearly weighted, and individuallyweighted; and wherein each of the sequence of Sr_(MSP) ^(N) signals andeach of the sequence of Sr_(LSP) ^(L) signals are biased from a commonreference bias network (RBN). Further aspects of the non-lineardigital-to-analog conversion (NDAC) method in an integrated circuit, themethod further comprising: wherein a plurality of the at least oneSo_(N) signal has a square profile; wherein a p-channel So_(N) signal,of the plurality of So_(N) signals, is responsive to a p-channel D word;wherein a q-channel So_(N) signal, of the plurality of So_(N) signals,is responsive to a q-channel D word; wherein the p-channel So_(N) andthe q-channel So_(N) signals are subtracted from one another to generatea scaled So_(xy) signal; wherein the p-channel D word is comprised of ascaled X digital word and a scaled Y digital word that are added to oneanother; wherein the q-channel D word is comprised of a scaled Y digitalword and a scaled Y digital word that are subtracted from one another;and wherein the scaled So_(xy) signal is proportional to the S_(R), andis an analog representation of a scaled multiplication product of thescaled X digital word and the scaled Y digital word.

Another aspect of the present disclosure is a non-lineardigital-to-analog converter (NDAC) system in an integrated circuit, thesystem comprising: a first non-linear Digital-to-Analog-Converter(DAC_(QM)), the DAC_(QM) including a digital input port (D_(QM)), ananalog output port (Ao_(QM)), and an analog reference input port(Ar_(QM)); a first linear Digital-to-Analog-Converter (DAC_(1L)), theDAC_(1L) having a digital input port (D_(1L)), an analog output port(Ao_(1L)), and an analog reference input port (Ar_(1L)); a second linearDigital-to-Analog-Converter (DAC_(2L)), the DAC_(2L) having a digitalinput port (D_(2L)), an analog output port (Ao_(2L)), and an analogreference input port (Ar_(2L)); a digital input word (D) comprised of aMost-Significant-Bits (MSB)s bank word (D_(MSP)), and aLeast-Significant-Bits (LSB)s bank word (D_(LSP)); a digital multiplier(X_(ML)), the X_(ML) having an M input digital word port (M), an N inputdigital word port (N), and an output digital word port (M×N); the M portcoupled to the D_(MSP) bank word; the N port coupled to the D_(LSP) bankword; the D_(1L) port coupled to the output digital word port M×N; theD_(2L) port coupled to the digital word N port; the D_(QM) port coupledto the digital word M port; wherein a first reference signal (Sr_(QM))is coupled to the Ar_(QM) port; wherein a second reference signal(Sr_(1L)) is coupled to the Ar_(1L) port; wherein a third referencesignal (Sr_(2L)) is coupled to the Ar_(2L) port; wherein a sum ofsignals at the Ao_(1L) and Ao_(2L) ports is a straight-lineapproximation between non-linear segments of a signal at the Ao_(QM)port; wherein a sum of signals at the Ao_(QM), Ao_(1L), and Ao_(2L)ports generates a non-linear analog output signal (So_(N)) at an analogoutput port Ao_(N); wherein an analog reference signal (S_(R)) isproportionally scaled to an Sr_(QM), the Sr_(1L), and the Sr_(2L)signals; wherein a sequence of non-linear reference signals (Sr_(MSP)^(N)), which form a transfer function of the DAC_(QM), are proportionalto the S_(R) signal; wherein the sequence of Sr_(MSP) ^(N) signals areat least one of squarely weighted, logarithmically weighted,non-linearly weighted, and individually weighted; wherein a sequence oflinear reference signals (Sr_(LSP) ^(L)), which form a transfer functionof the DAC_(1L) and DAC_(2L), are proportional to the S_(R) signal;wherein the sequence of Sr_(LSP) ^(L) signals are at least one of binaryweighted, linearly weighted, and individually weighted; and wherein theSo_(N) signal substantially follows one of a square, logarithmic, andnon-linear profile, is proportional to the S_(R) signal, and responsiveto the D word. Further aspects of the non-linear digital-to-analogconverter (NDAC) system in an integrated circuit, the system furthercomprising: wherein the sequence of Sr_(MSP) ^(N) signals, and thesequence of Sr_(LSP) ^(L) signals, are biased from a common referencebias network (RBN). Further aspects of the non-linear digital-to-analogconverter (NDAC) system in an integrated circuit, the system furthercomprising: a plurality of So_(N) signals having a square profile;wherein a p-channel So_(N) signal, of the plurality of So_(N) signals,is responsive to a p-channel D word; wherein a q-channel So_(N) signal,of the plurality of So_(N) signals, is responsive to a q-channel D word;wherein the p-channel So_(N) and the q-channel So_(N) signals aresubtracted from one another to generate a scaled So_(xy) signal; whereinthe p-channel D word is comprised of a scaled X digital word and ascaled Y digital word that are added to one another; wherein theq-channel D word is comprised of a scaled Y digital word and a scaled Ydigital word that are subtracted from one another; and wherein thescaled So_(xy) signal is proportional to the S_(R), and is an analogrepresentation of a scaled multiplication product of the scaled Xdigital word and the scaled Y digital word. Further aspects of thenon-linear digital-to-analog converter (NDAC) system in an integratedcircuit, the system further comprising: the Ao_(QM) port, Ao_(1L) port,and Ao_(2L) port are coupled to an output port Ao_(Q); and wherein theDAC_(QM), DAC_(1L), and DAC_(2L) operate in current mode.

Another aspect of the present disclosure is a non-lineardigital-to-analog converter (NDAC) system in an integrated circuit, thesystem comprising: a first non-linear digital-to-analog-converter(DAC_(QM)), the DAC_(QM) having a digital input port (D_(QM)), an analogoutput port (Ao_(QM)), and an analog reference input port (Ar_(QM)); afirst linear digital-to-analog-converter (DAC_(1L)), the DAC_(1L) havinga digital input port (D_(1L)), an analog output port (Ao_(1L)), and ananalog reference input port (Ar_(1L)); a second lineardigital-to-analog-converter (DAC_(2L)), the DAC_(2L) having a digitalinput port (D_(2L)), an analog output port (Ao_(2L)), and an analogreference input port (Ar_(2L)); a digital input word (D) comprised of aMost-Significant-Bits (MSB)s bank word (D_(MSP)) and aLeast-Significant-Bits (LSB)s bank word (D_(LSP)); an MSB bank port (M)coupled to the D_(MSP) word; an LSB bank port (N) coupled to the D_(LSP)word; the D_(1L) port coupled to the M port; the D_(2L) port coupled tothe N port; the D_(QM) port coupled to the M port; wherein a firstreference signal (Sr_(QM)) is coupled to the Ar_(QM) port; wherein asecond reference signal (Sr_(1L)) is coupled to the Ar_(1L) port;wherein a signal at the Ao_(1L) port (So_(1L)) is combined with a thirdreference offset signal (Sfr_(2L)) and combination of which is coupledto the Ar_(2L) port; wherein a signal at the Ao_(2L) port is astraight-line approximation between non-linear segments of a signal atthe Ao_(QM) port; wherein a sum of signals at the Ao_(QM) and theAo_(2L) ports generates a non-linear analog output signal (So_(N)) at ananalog output port Ao_(N); wherein an analog reference signal (S_(r)) isproportionally scaled to the Sr_(QM), the Sr_(1L), and the Sr_(2L)signals; wherein a sequence of non-linear reference signals (Sr_(MSP)^(N)), which form the transfer function of the DAC_(QM), areproportional to the S_(R) signal; wherein the sequence of Sr_(MSP) ^(N)signals are at least one of squarely weighted, logarithmically weighted,non-linearly weighted, and individually weighted; wherein the sequenceof linear reference signals (Sr_(LSP) ^(L)), which form the transferfunction of the DAC_(1L) are proportional to the S_(R) signal; whereinthe sequence of Sr_(LSP) ^(L) signals are at least one of binaryweighted, linearly weighted, and individually weighted; and wherein theSo_(N) signal substantially follows one of a square, logarithmic, andnon-linear profile, is proportional to the S_(R) signal, and responsiveto the D word. Further aspects of the non-linear digital-to-analogconverter (NDAC) system in an integrated circuit, the system furthercomprising: wherein each of the sequence of Sr_(MSP) ^(N) signals, andeach of the sequence of Sr1 _(LSP) ^(L) signals are biased from a commonreference bias network (RBN). Further aspects of the non-lineardigital-to-analog converter (NDAC) system in an integrated circuit, thesystem further comprising a plurality of So_(N) signals having a squareprofile; wherein a p-channel So_(N) signal, of the plurality of So_(N)signals, is responsive to a p-channel D word; wherein a q-channel So_(N)signal, of the plurality of So_(N) signals, is responsive to a q-channelD word; wherein the p-channel So_(N) and the q-channel So_(N) signalsare subtracted from one another to generate a scaled So_(xy) signal;wherein the p-channel D word is comprised of a scaled X digital word anda scaled Y digital word that are added to one another; wherein theq-channel D word is comprised of a scaled Y digital word and a scaled Ydigital word that are subtracted from one another; and wherein thescaled So_(xy) signal is proportional to the S_(R) and is an analogrepresentation of a scaled multiplication product of the scaled Xdigital word and the scaled Y digital word.

Further aspects of the non-linear digital-to-analog converter (NDAC)system in an integrated circuit, the system further comprising: theAo_(QM) port and Ao_(2L) port are coupled to an output port Ao_(Q); andwherein the DAC_(QM), DAC_(1L), and DAC_(2L) operate in current mode.

Another aspect of the present disclosure is a non-lineardigital-to-analog converter (NDAC) system in an integrated circuit, thesystem comprising: a first non-linear Digital-to-Analog-Converter(DAC_(QM)), the DAC_(QM) having a digital input port (D_(QM)), an analogoutput port (Ao_(QM)), and an analog reference input port (Ar_(QM)); afirst linear Digital-to-Analog-Converter (DAC_(1L)), the DAC_(1L) havinga digital input port (D_(1L)), an analog output port (Ao_(1L)), and ananalog reference input port (Ar_(1L)); a linearly meshed digital-inputto analog-output multiplier (mDiSo_(LSP) ^(L)), the mDiSo_(LSP) ^(L)having an M digital input port (M) and a N digital port (N), an analogoutput port (Ao_(2L)), and an analog reference input port (Ar_(2L)); adigital input word (D) comprised of a Most-Significant-Bits (MSB)s bankword (D_(MSP)) and a Least-Significant-Bits (LSB)s bank word (D_(LSP));the M port coupled to the D_(MSP) word; the N port coupled to the A_(sp)word; the D_(1L) port coupled to the N port; the D_(QM) port coupled tothe M port; wherein a first reference signal (Sr_(QM)) is coupled to theAr_(QM) port; wherein a second reference signal (Sr_(1L)) is coupled tothe Ar_(1L) port; wherein a third reference signal (Sr_(2L)) is coupledto the Ar_(2L) port; wherein a sum of signals at the Ao_(1L) and Ao_(2L)ports is a straight-line approximation between non-linear segments of asignal at the Ao_(QM) port; wherein a sum of signals at the Ao_(QM),Ao_(1L), and Ao_(2L) ports generates a non-linear analog output signal(So_(N)) at an analog output port Ao_(N); wherein an analog referencesignal (S_(R)) is proportionally scaled to the Sr_(QM), the Sr_(1L), andthe Sr_(2L) signals; wherein a sequence of non-linear reference signals(Sr_(MSP) ^(N)), which form the transfer function of the DAC_(QM), areproportional to the S_(R) signal, wherein the sequence of Sr_(MSP) ^(N)signals are at least one of squarely weighted, logarithmically weighted,non-linearly weighted, and individually weighted; wherein the sequenceof linear reference signals (Sr_(LSP) ^(L)), which form the transferfunctions of the DAC_(1L) and the mDiSo_(LSP) ^(L), are proportional tothe S_(R) signal; wherein the sequence of Sr_(LSP) ^(L) signals are atleast one of binary weighted, linearly weighted, and individuallyweighted; wherein the So_(N) signal substantially follows one of asquare, logarithmic, and non-linear profile, is proportional to theS_(R) signal, and responsive to the D word. Further aspects of thenon-linear digital-to-analog converter (NDAC) system in an integrated,the system further comprising: wherein each of the sequence of Sr_(MSP)^(N) signals, each of the sequence of Sr1 _(LSP) ^(L) signals, and eachof the sequence of Sr2 _(LSP) ^(L) signals are biased from a commonreference bias network (RBN). Further aspects of the non-lineardigital-to-analog converter (NDAC) system in an integrated circuit, thesystem further comprising: a plurality of So_(N) signals having a squareprofile; wherein a p-channel So_(N) signal, of the plurality of So_(N)signals, is responsive to a p-channel D word; wherein a q-channel So_(N)signal, of the plurality of So_(N) signals, is responsive to a q-channelD word; wherein the p-channel So_(N) and the q-channel So_(N) signalsare subtracted from one another to generate a scaled So_(xy) signal;wherein the p-channel D word is comprised of a scaled X digital word anda scaled Y digital word that are added to one another; wherein theq-channel D word is comprised of a scaled Y digital word and a scaled Ydigital word that are subtracted from one another; and wherein thescaled So_(xy) signal is proportional to the S_(R), and is an analogrepresentation of a scaled multiplication product of the scaled Xdigital word and the scaled Y digital word. Further aspects of thenon-linear digital-to-analog converter (NDAC) system in an integratedcircuit, the system further comprising: the Ao_(QM) port, Ao_(1L) port,and Ao_(2L) port are coupled to an output port Ao_(Q); and wherein theDAC_(QM), DAC_(1L), and DAC_(2L) operate in current mode.

Another aspect of the present disclosure is a multiple channelcurrent-mode data converter method in an integrated circuit, the methodcomprising: generating a sequence of reference bias current signals(Si_(Rb)) from a reference bias network (RBN); mirroring the sequence ofSi_(Rb) signals from the RBN into at least one iDC; wherein the scalingof the mirroring of the sequence of Si_(Rb) signals from the RBN into atleast one iDC, is individually scaled; wherein the sequence of Si_(Rb)signals from the RBN is weighted at least equally, binarily,non-linearly, and individually; wherein each Si_(Rb) signal from thesequence of Si_(Rb) signals from the RBN is scaled proportionately to areference current signal (S_(R)); wherein each Si_(Rb) signal from thesequence of Si_(Rb) signals from the RBN is mirrored from the S_(R)signal; wherein the sequence of Si_(Rb) signals, from the RBN in the atleast one iDC, program the reference current network of the at least oneiDC, which establishes the input-to-output transfer function of the atleast one iDC; wherein the at least one iDC is at least one ofcurrent-mode Digital-to-Analog-Converter (iDAC) and current-modeAnalog-to-Digital-Converter (iADC); wherein if the at least one iDCincludes an iDAC, then the analog output current signal of each iDAC isproportional to the S_(R) signal received by that iDAC, and responsiveto a digital input word received by that iDAC; and wherein if the atleast one iDC includes an iADC, then a digital output word of each iADCis responsive to the analog input current signal of that iADC andproportional to the S_(R) signal received by that iADC. Further aspectsof the multiple channel current-mode data converter method in anintegrated circuit, the method further comprising: regulating the S_(R)signal from the RBN; wherein the analog ports of the at least one iDCsubstantially track power supply voltage variations; and wherein if theat least one iDC includes an iDAC, then the analog output current signalof each iDAC is substantially desensitized with respect to power supplyvariations; and wherein if the at least one iDC includes an iADC, then adigital output word of each iADC is substantially desensitized withrespect to power supply variations. Further aspects of the multiplechannel current-mode data converter method in an integrated circuit, themethod further comprising: wherein if the at least one iDC includes aniDAC: generating at least one pair of current output signals (S_(X) andS_(Y)) from at least one pair of iDACs (iDAC_(X), and iDAC_(Y)), thatare proportional to the S_(R) signal, and responsive to the respectivedigital input words (D_(X) and D_(Y)) of the at least one pair of iDACs;receiving the at least one pair of S_(X) and S_(Y) signals,respectively, into current input ports A_(mX) and A_(mY) of at least oneanalog current multiplier (iMULT); receiving at least one Si_(Rb) signalfrom the sequence Si_(Rb) signals from the RBN into a reference currentinput port (A_(mR)) of the at least one iMULT; and wherein aninput-output transfer function of the at least one iMULT follows therelationship S_(Y)/S_(R)=S_(X)/S_(X), and wherein S_(O) signal is atleast one output current signal of the at least one iMULT. Furtheraspects of the multiple channel current-mode data converter method in anintegrated circuit, the method further comprising: wherein at least oneof S_(R), S_(Y), S_(X), and S_(O) signals is generated without cascode.Further aspects of the multiple channel current-mode data convertermethod in an integrated circuit, the method further comprising: whereinthe respective voltages at A_(mR) and A_(mY) ports track power supplyvoltage variations in substantial proportion to one another; wherein therespective voltages at A_(mX) and A_(mO) ports track power supplyvoltage variations in substantial proportion to one another; and whereinthe at least one S_(O) signal of the at least one iMULT is substantiallyinsensitive to power supply voltage variations. Further aspects of themultiple channel current-mode data converter method in an integratedcircuit, the method further comprising: wherein if the at least one iDCincludes an iDAC: wherein the sequence of Si_(Rb) signals from the RBNis weighted squarely; summing at least one pair of digital input words(D_(x) and D_(y)) together to generate at least a scaled D_(x+y) digitalword; subtracting the at least one pair of digital input words D_(x) andD_(y) from one another to generate at least one scaled D_(x−y) digitalword; receiving at least one pair of scaled digital input words (D_(x+y)and D_(x−y)) respectively into each of at least one pair of iDACs(iDAC_((x+y)) ₂ and iDAC_((x−y)) ₂ ); generating at least one pair ofcurrent output signals (S_((x+y)) ₂ and S_((x−y)) ₂ ) that areproportional to the S_(R), and responsive to the at least one pair ofthe scaled D_(x+y) and D_(x−y) words of the at least one pair ofiDAC_((x+y)) ₂ and iDAC_((x−y)) ₂ ; subtracting from one another, eachof the S_((x+y)) ₂ and S_((x−y)) ₂ signals of the at least one pair ofiDACs (iDAC_((x+y)) ₂ and iDAC_((x−y)) ₂ ), to generate at least onemultiplicand output current signal (S_(iMULT)), wherein S_(iMULT) is theanalog representation of a scaled product digital word (D_(x)×D_(y)).Further aspects of the multiple channel current-mode data convertermethod in an integrated circuit, the method further comprising: whereinif the at least one iDC includes an iDAC: wherein the sequence ofSi_(Rb) signals from the RBN is weighted logarithmically; receiving atleast one pair of digital input words (D_(X) and D_(Y)) respectivelyinto at least one pair of the iDACs (iDAC_(log X), and iDAC_(log Y));generating at least one pair of current output signals (S_(log X) andS_(log Y)) that are proportional to the S_(R) signal, and responsive tothe at least one pair of D_(x) and D_(y) words; and summing theS_(log X) and S_(log Y) signals to generate at least one multiplicandoutput current (S_(logMULT)), wherein S_(logMULT) is the analogrepresentation of a digital logarithmic word (log D_(x)×D_(y)).

Another aspect of the present disclosure is a power supplydesensitization method in a current-mode digital-to-analog converter(iDAC) in an integrated circuit, the method comprising: receiving adigital input word (D_(X)) into a x-channel iDAC (iDAC_(X)) having ananalog output current signal (S_(X)), and a reference input signal(S_(RX)), wherein the iDAC_(X) is without cascodes; receiving a digitalinput word (D_(Y)) into a y-channel iDAC (iDAC_(Y)) having an analogoutput current signal (S_(Y)), and a reference input signal (S_(RY)),wherein the iDAC_(Y) is without cascodes; receiving the S_(X) signalinto an input port of a power supply desensitization (PSR) circuit;regulating and generating the S_(RY) reference input signal at an outputport of the PSR circuit, wherein the S_(Y) signal is desensitized frompower supply variations; and generating a multiplicand output current(S_(iMULT)) at the S_(Y) signal, wherein the S_(iMULT) signal is ananalog representation of the product of the D_(X) and D_(Y) digitalwords.

Another aspect of the present disclosure is a multiple channelcurrent-mode data converter system in an integrated circuit, the methodcomprising: a Metal-Oxide-Semiconductor-Field-Effect-Transistors(MOSFET)s each having a gate-port, a drain-port, and a source port, andeach having a scale (W/L); a sequence of diode-connected MOSFETs,wherein the gate port and the drain port of each MOSFET in the sequenceof the MOSFET are coupled together and coupled to a sequence ofgate-drain ports; at least one current-mode Data-Converter (iDC), whoseinput-output transfer function profiles is programmed by a network ofcurrent reference signals of the at least one iDC, wherein the networkof current reference signals of the at least one iDC is the network ofsequence of signals at a sequence of drain ports of a sequence ofmirroring MOSFETs; the sequence of gate-drain ports of the sequence ofdiode-connected MOSFETs coupled to a sequence of gate ports of themirroring MOSFETs; wherein each S_(sR) signal in a sequence of S_(sR)signals is proportional to a current reference signal (S_(R)); whereinthe sequence of S_(sR) signals is coupled to the respective sequence ofgate-drain ports of sequence of diode-connected MOSFETs; wherein thesequence of scaled S_(sR) signals are scaled at least one of equallyweighted currents, binarily weighted currents, non-linear weighted, andindividually weighted currents; wherein the W/L scale of each MOSFET isprogrammed individually; wherein the iDC is at least one of current-modeDigital-to-Analog-Converter (iDAC) and current-modeAnalog-to-Digital-Converter (iADC); wherein if the at least one iDCincludes an iDAC, then the analog output current signal of each iDAC isproportional to the S_(R) signal received by that iDAC, and responsiveto a digital input word received by that iDAC; and wherein if the atleast one iDC includes an iADC, then a digital output word of each iADCis responsive to the analog input current signal of that iADC andproportional to the S_(R) signal received by that iADC.

Another aspect of the present disclosure is a multiple channelcurrent-mode data converter system in an integrated circuit, the systemcomprising: a sequence of current mirrors (iCM), each iCM having acurrent mirror input port (Ai_(iCM)) for receiving a sequence of scaledreference current signals S_(R), a current mirror output port(Ao_(iCM)), and an input-to-output gain factor (G_(iCM)); a current modedata converter (iDC) having a sequence of reference input ports(Ar_(iDC)); the Ao_(iCM) port of each of the sequence of iCMs coupled tothe respective Ar_(iDC) port of the sequence of Ar_(iDC) ports of theiDC; wherein each scaled reference current S_(R) of a sequence of scaledS_(R) signals is coupled respectively to the Ai_(iCM) port of each iCMof the sequence of iCMs; wherein the G_(iCM) of each iCM of the sequenceof iCM is programmed individually; wherein the iDC is at least one ofcurrent-mode Digital-to-Analog-Converter (iDAC), and current-modeAnalog-to-Digital-Converter (iADC); wherein the sequence of scaled S_(R)signals are scaled at least one of equally weighted currents, binarilyweighted currents, non-linear weighted currents, and individuallyweighted currents; wherein if one or more iDC includes an iDAC, then theanalog output current signal of each iDAC is proportional to the S_(R)signal received by that iDAC, and responsive to a digital input wordreceived by that iDAC; and wherein if one or more iDC includes an iADC,then a digital output word of each iADC is responsive to the analoginput current signal of that iADC and proportional to the S_(R) signalreceived by that iADC.

Another aspect of the present disclosure is a multiple channelcurrent-mode data converter system in an integrated circuit, the systemcomprising: a sequence of current mirrors (iCM), each iCM having acurrent mirror input port (Ai_(iCM)) for receiving a sequence of scaledreference current signals (S_(R))s, a current mirror output port(Ao_(iCM)), and an input-to-output gain factor (G_(iCM)); one or morecurrent mode data converters (iDC), each of the one or more iDCs havinga sequence of reference input ports (Ar_(iDC)); each of the one or moreAo_(iCM) ports of each iCM of the sequence of iCMs respectively coupledto the Ar_(iDC) port of the sequence of Ar_(iDC) ports of the one ormore iDCs; wherein each scaled S_(R) signal of a sequence of scaledS_(R) signals is coupled respectively to the Ai_(iCM) port of each iCMof the sequence of iCMs; wherein the G_(iCM) of each iCM of the sequenceof iCMs is programmed individually; wherein the one or more iDCs is atleast one of a current-mode Digital-to-Analog-Converter (iDAC), and acurrent-mode Analog-to-Digital-Converter (iADC); wherein the sequence ofscaled S_(R) signals are scaled at least one of equally weightedcurrents, binarily weighted currents, non-linear weighted currents, andindividually weighted currents; wherein if one or more iDC includes aniDAC, then the analog output current signal of each iDAC is proportionalto the S_(R) signal received by that iDAC, and responsive to a digitalinput word received by that iDAC; and wherein if one or more iDCincludes an iADC, then a digital output word of each iADC is responsiveto the analog input current signal of that iADC and proportional to theS_(R) signal received by that iADC.

Another aspect of the present disclosure is a multiple channelcurrent-mode data converter system in an integrated circuit, the systemcomprising: a sequence of Current-Controlled-Voltage-Sources (CCVS)s,each CCVS in the sequence of the CCVSs having an input current port(Ai_(ccvs)) for receiving a sequence of scaled reference current signals(S_(R))s, an output port (Ao_(ccvs)) for providing an output voltagesignal (So_(ccvs)), and an input-current to output-voltage gain factor(G_(ccvs)); a plurality of current mode data converters (iDC); each iDCof the plurality of iDCs having a sequence ofVoltage-Controlled-Current-Sources (VCCS)s; each VCCS of the sequence ofVCCSs, in each iDC of the plurality of iDCs, having an input voltageport (Ai_(ccvs)), an output current port (Ao_(ccvs)) for providing anoutput current signal (So_(ccvs)), and an input-voltage tooutput-current gain factor (G_(ccvs)); each Ao_(ccvs) port of thesequence of CCVSs, respectively coupled to each Ai_(ccvs) port of thesequence of VCCSs, in each iDC of the plurality of iDCs; wherein eachscaled S_(R) source of a sequence of scaled S_(R) sources is coupledrespectively to the Ai_(ccvs) port of each CCVS of the sequence ofCCVSs; wherein the sequence of VCCS in each iDC arranges the referencecurrent network of each respective iDC which establishes theinput-to-output transfer function of each respective iDC; wherein theG_(ccvs) of each CCVS of the sequence of CCVSs is programmedindividually; wherein the G_(ccvs) of each VCCS of the sequence of VVCSsin each iDC of the plurality of iDCs is programmed individually; whereinthe one or more iDC of each iDC of the plurality of iDCs is at least oneof a current-mode Digital-to-Analog-Converter (iDAC), and a current-modeAnalog-to-Digital-Converter (iADC); wherein the sequence of scaled S_(R)sources are scaled at least one of equally weighted currents, binarilyweighted currents, non-linear weighted currents, and individuallyweighted currents; wherein if one or more iDC includes an iDAC, then theanalog output current signal of each iDAC is proportional to the S_(R)signal received by that iDAC, and responsive to a digital input wordreceived by that iDAC; and wherein if one or more iDC includes an iADC,then a digital output word of each iADC is responsive to the analoginput current signal of that iADC and proportional to the S_(R) signalreceived by that iADC.

Another aspect of the present disclosure is a multiple channelcurrent-mode data converter method in an integrated circuit, the methodcomprising: generating a sequence of reference bias current signals(Si_(Rb)); receiving the sequence of Si_(Rb) signals into a sequence ofCurrent-Controlled-Voltage-Sources (CCVS)s to generate a sequence ofreference bias voltage signals (Sv_(Rb)); receiving the sequence ofSv_(Rb) signals into at least one sequence ofVoltage-Controlled-Current-Sources (VCCS)s in at least one current modedata converter (iDC), wherein the at least one sequence of VCCSsreplicates the sequence of Si_(Rb) signals; wherein the sequence ofSi_(Rb) signals is weighted at least one of equally, binarily,non-linearly, and individually, and wherein each S_(Rb) signal is scaledproportionately to a reference current signal (S_(R)); wherein thesequence of VCCS in the at least one iDC arranges the reference currentnetwork of each respective iDC which establishes the input-to-outputtransfer function of each respective iDC; wherein the at least one iDCis at least one of current-mode Digital-to-Analog-Converter (iDAC) andcurrent-mode Analog-to-Digital-Converter (iADC); wherein the analogoutput current signal of the iDAC is proportional to S_(R) signal andresponsive to the digital input word of the iDAC; wherein the digitaloutput word of the at least one iADC is responsive to the analog inputcurrent signal of the at least one iADC and proportional to the S_(R)signal; wherein if the at least one iDC includes an iDAC, then theanalog output current signal of each iDAC is proportional to the S_(R)signal received by that iDAC, and responsive to a digital input wordreceived by that iDAC; and wherein if the at least one iDC includes aniADC, then a digital output word of each iADC is responsive to theanalog input current signal of that iADC and proportional to the S_(R)signal received by that iADC.

Another aspect of the present disclosure is a meshed multiplier systemin an integrated circuit, the system comprising: a first digital inputport having a of width of M bits of a first digital input word D_(X); asecond digital input port having a width of N bits of a second digitalinput word D_(Y); a plurality of N scaled current source banks, eachscaled current source bank uniquely corresponding to a bit of D_(Y);each of the N scaled current source banks comprising a plurality of Mscaled current sources, each scaled current source having acorresponding first switch and a corresponding second switch, eachcurrent source uniquely corresponding to a bit of the first digitalinput word D_(X); each scaled current source in each scaled currentsource bank coupled to an input of its corresponding first switch, thefirst switch responsive to the bit of the first digital input word D_(X)corresponding to the scaled current source; the first switch having anoutput coupled to an input of its corresponding second switch, thesecond switch responsive to the bit of the second digital input wordD_(Y) corresponding to the scaled current source bank; the second switchhaving an output coupled to an output node; wherein the N scaled currentsource banks, are at least one of binarily weighted, linearly weighted,and individually weighted; wherein the plurality of M scaled currentsources in each scaled current source bank, are at least one of binarilyweighted, linearly weighted, and individually weighted; and wherein M isless than 17, and N is less than 17. Further aspects of the meshedmultiplier system in an integrated circuit, the system furthercomprising: wherein M and N are equal.

Another aspect of the present disclosure is a meshed multiplier methodin an integrated circuit, the method comprising: receiving a firstdigital input word D_(X) of width of M bits, wherein M is less than 17;receiving a second digital input word D_(Y) of width of N bits, whereinN is less than 17; activating one bank of N banks of M scaled currentsources responsive to a bit of D_(Y) corresponding to the one bank of Nbanks, thereby activating each of the M scaled current sources;receiving current into an output node from one of the activated M scaledcurrent sources responsive to a corresponding bit of D_(X). Furtheraspects of the meshed multiplier system in an integrated circuit, thesystem further comprising: wherein M and N are equal.

Another aspect of the present disclosure is a meshed digital-input toanalog current-output multiplier system in an integrated circuit, thesystem comprising: a digital-input to analog-output multiplier(XD_(i)I_(o)) comprised of a Ao_(XY) port, a first digital input port(D_(X)) wherein the D_(X) port is M-bit wide, a second digital inputport (D_(Y)) wherein the D_(Y) port is N-bit wide, and a reference portfor receiving a S_(Ru) signal; the XD_(i)I_(o) comprising: a sequence ofM meshed digital-input to analog current-output sub-multipliers(mD_(i)I_(o)), wherein each mD_(i)I_(o) is comprised of a first switchbank (iSW₁ ^(B)), a second switch bank (iSW₂ ^(B)), a current referencesignals bank (S_(R) ^(B)), and a first digital 1-bit wide port (B_(M));for each mD_(i)I_(o), each iSW₁ ^(B) switch bank comprised of a sequenceof N switches, wherein the N control-ports of the N switches coupledtogether, and coupled to a 1-bit wide B_(M) port; for each mD_(i)I_(o),each iSW₂ ^(B) switch bank comprised of a sequence of N switches,wherein the gate-ports respectively coupled to the D_(Y) port. for eachmD_(i)I_(o), the output ports of the first sequence of N switches of theiSW₁ ^(B) switch bank coupled to the input ports of the second sequenceof N switches of the iSW₂ ^(B) switch bank; for each mD_(i)I_(o), eachS_(R) ^(B) signal bank comprised of a sequence of N current referencesignal ports (A_(R)) for receiving sequence of N scaled currentreference signals (S_(R)), wherein the sequence of N scaled S_(R)signals is at least one of binarily weighted, linearly weighted, andindividually weighted, and wherein each scaled S_(R) signal isproportional to the S_(Ru) signal; for each mD_(i)I_(o), the sequence ofN scaled S_(R) sources of the S_(R) ^(B) signal banks coupledrespectively to the sequence of N input ports of the iSW₁ ^(B) switchbank; for each mD_(i)I_(o), the sequence of N output ports of the iSW₂^(B) switch bank coupled to the Ao_(XY) port; for each mD_(i)I_(o), thesequence of M 1-bit wide B_(M) ports coupled to the respective M-bitwide D_(X) ports; wherein for each mD_(i)I_(o), a sum of the sequence ofN of scaled S_(R) sources of the S_(R) ^(B) banks is at least one ofbinarily weighted, linearly weighted, and individually weighted; andwherein the XD_(i)I_(o) generates an analog multiplicand signal at theAo_(XY) port, that is proportional to the S_(Ru) signal, and responsiveto the multiplication product of digital words at the D_(X) and theD_(Y) ports.

Further aspects of the meshed digital-input to analog current-outputmultiplier system in an integrated circuit, the system furthercomprising: a plurality of the XD_(i)I_(o); the Ao_(XY) port from eachof the plurality of XD_(i)I_(o)s coupled to an Ao_(MAC) port; wherein asignal through the Ao_(MAC) port is a multiply-accumulate current signal(So_(MAC)), wherein the So_(MAC) signal is a summation of signalsthrough the plurality of Ao_(XY) ports; and wherein the So_(MAC) isproportional to the S_(Ru) source and responsive to a plurality ofdigital words that are the multiplication product of pairs of digitalwords inputted to a plurality of pairs of D_(X) and D_(Y) ports. Furtheraspects of the meshed digital-input to analog current-output multipliersystem in an integrated circuit, the system further comprising: a biascurrent-mode Digital-to-Analog-Converter (iDAC) for generating a biascurrent signal (S_(B)), the bias current signal (S_(B)) coupled to theSo_(MAC) signal to generate a biased multiply-accumulate current signal(So_(BMAC)), wherein the So_(BMAC) signal is the summation of theSo_(MAC) signal and the S_(B) signal. Further aspects of the mesheddigital-input to analog current-output multiplier system in anintegrated circuit, the system further comprising: a current-modeAnalog-to-Digital Converter (iADC) for digitizing the So_(BMAC) signalto generate a Do_(BMAC) word that is a digital representation of theSo_(BMAC) signal. Further aspects of the meshed digital-input to analogcurrent-output multiplier system in an integrated circuit, the systemfurther comprising: each scaled S_(R) source, of the sequence of Nscaled S_(R) sources of each of the S_(R) ^(B) signal bank of eachmD_(i)I_(o), is biased from a common reference bias network (RBN).Further aspects of the meshed digital-input to analog current-outputmultiplier system in an integrated circuit, the system furthercomprising: a Metal-Oxide-Semiconductor-Field-Effect-Transistors(MOSFET)s each having a gate-port, a drain-port, and a source port, andeach having a scale (W/L); and each switch, of the iSW₁ ^(B) switch bankof each mD_(i)I_(o), is a MOSFET wherein the input of the switch is thesource-port of the MOSFET, the output of the switch is the drain-port ofthe MOSFET, and the control port of the switch is the gate-port of theMOSFET.

Another aspect of the present disclosure is a meshed digital-input toanalog current-output multiplier system in an integrated circuit, thesystem comprising: a digital-input to analog-output multiplier(XD_(i)I_(o)) comprised of a Ao_(XY) port, a first digital input port(D_(X)) wherein the D_(X) port is w-bit wide, a second digital inputport (D_(t)) wherein the D^(Y) port is z-bit wide, and a reference inputport for receiving a S_(R) signal; the XD_(i)I_(o) comprising: aplurality of Metal-Oxide-Semiconductor-Field-Effect-Transistors(MOSFET)s, each having a gate-port, a drain-port, and a source port, andeach having a scale (W/L); a sequence of M meshed digital-input toanalog current-output sub-multipliers (mD_(i)I_(o)), wherein eachmD_(i)I_(o) is comprised of a first MOSFET bank (M₁ ^(B)), a secondMOSFET bank (M₂ ^(B)), a current reference signals bank (S_(R) ^(B)),and a first digital 1-bit wide port (B_(W)); for each mD_(i)I_(o), eachM₁ ^(B) comprised of a sequence of z MOSFETs, the gate-ports of the zMOSFETs coupled together, and coupled to a 1-bit wide B_(M) port; foreach mD_(i)I_(o), each M₂ ^(B) comprised of a sequence of z MOSFETs, thegate-ports respectively coupled to the D_(Y) port; for each mD_(i)I_(o),the drain ports of the first sequence of z MOSFETs coupled to the sourceports of the second sequence of z MOSFETs; for each mD_(i)I_(o), eachS_(R) ^(B) signal bank comprised of a sequence of z current referencesignal ports (A_(R)) for receiving z sequence of scaled currentreference signals (S_(R)), wherein the sequence of z scaled S_(R)signals is at least one of binarily weighted, linearly weighted, andindividually weighted, and wherein each scaled S_(R) signal isproportional to the S_(Ru) signal; for each mD_(i)I_(o), the sequence ofz scaled S_(R) ^(B) sources of the S_(R) ^(B) signal banks coupledrespectively to the sequence of z input ports of the M₂ ^(B) switchbank; for each mD_(i)I_(o), the sequence of z output ports of the MYswitch bank coupled to the Ao_(XY) port; for each mD_(i)I_(o), thesequence of w 1-bit wide B_(W) ports coupled to the respective w-bitD_(X) ports; wherein for each mD_(i)I_(o), a sum of the sequence of z ofscaled S_(R) sources of the S_(R) ^(B) banks is at least one of binarilyweighted, linearly weighted, and individually weighted; and wherein theXD_(i)I_(o) generates an analog multiplicand signal at the Ao_(XY) port,that is proportional to the S_(Ru) signal, and responsive to themultiplication product of digital words at the D_(X) and the D_(Y)ports.

DETAILED DESCRIPTION

Numerous embodiments are described in the present application and arepresented for illustrative purposes only and is not intended to beexhaustive. The embodiments were chosen and described to explainprinciples of operation and their practical applications. The presentdisclosure is not a literal description of all embodiments of thedisclosure(s). The described embodiments also are not, and are notintended to be, limiting in any sense. One of ordinary skill in the artwill recognize that the disclosed embodiment(s) may be practiced withvarious modifications and alterations, such as structural, logical, andelectrical modifications. For example, the present disclosure is not alisting of features which must necessarily be present in allembodiments. On the contrary, a variety of components are described toillustrate the wide variety of possible embodiments of the presentdisclosure(s). Although particular features of the disclosed embodimentsmay be described with reference to one or more particular embodimentsand/or drawings, it should be understood that such features are notlimited to usage in the one or more particular embodiments or drawingswith reference to which they are described, unless expressly specifiedotherwise. The scope of the disclosure is to be defined by the claims.

Although process (or method) steps may be described or claimed in aparticular sequential order, such processes may be configured to work indifferent orders. In other words, any sequence or order of steps thatmay be explicitly described or claimed does not necessarily indicate arequirement that the steps be performed in that order. The steps ofprocesses described herein may be performed in any order possible.Further, some steps may be performed simultaneously despite beingdescribed or implied as occurring non-simultaneously (e.g., because onestep is described after the other step). Moreover, the illustration of aprocess by its depiction in a drawing does not imply that theillustrated process is exclusive of other variations and modificationsthereto, does not imply that the illustrated process or any of its stepsare necessary to the embodiment(s). In addition, although a process maybe described as including a plurality of steps, that does not imply thatall or any of the steps are essential or required. Various otherembodiments within the scope of the described disclosure(s) includeother processes that omit some or all of the described steps. Inaddition, although a circuit may be described as including a pluralityof components, aspects, steps, qualities, characteristics and/orfeatures, that does not indicate that any or all of the plurality areessential or required. Various other embodiments may include othercircuit elements or limitations that omit some or all of the describedplurality.

Consider that all the figures comprised of circuits, blocks, or systemsillustrated in this disclosure are powered up by positive and negativepower supplies, V_(DD) and V_(SS) (and V_(SS) can be connected to theground potential or zero volts for single supply applications),respectively (unless otherwise specified), and they are not shown forillustrative clarity of the disclosed figures. Terms FET isfield-effect-transistor; MOS is metal-oxide-semiconductor; MOSFET is MOSFET; PMOS is p-channel MOS; NMOS is n-channel MOS; BiCMOS is bipolarCMOS. Throughout this disclosure, the body terminal of NMOSFET can beconnected to the source terminal of NMOSFET or to V_(SS). Also, the bodyterminal of PMOSFET can be connected to the source terminal of PMOSFETor to V_(DD). The term V_(GS) is gate-to-source port voltage of aMOSFET. The term V_(DS) is drain-to-source port voltage of a MOSFET. Theterm I_(S) or I_(D) is drain current of a MOSFET. The term V_(A) is adevice parameter, and the early voltage a MOSFET.

All the data-converters including, analog-to-digital-converters (ADC) aswell as digital-to-analog-converters (DAC) may not show, forillustrative clarity, a positive reference and a negative referenceinput, where the negative reference input can be connected to the groundpotential or zero volts. A current-mode DAC is iDAC, and a current-modeADC is iADC. A current analog switch (iSW) has one input, one digitalcontrol signal, and either one or two output ports that receive the iSWinput signal. An iSW with two output ports, steer the iSW's input signalto either of iSW's output ports depending on the polarity of the iSWdigital control signal. An iSW with one output, steer the iSW's inputsignal to iSW's the positive output port or blocks it depending on thepolarity of the iSW digital control signal. Most-Significant-Bit is MSBand Least-Significant-Bit is LSB, pertaining to data-converters digitalbits. Most-Significant-Portion is MSP and Least-Significant-Portion isLSP, pertaining to the portions of signals represented by the MSB bankdigital-word and LSB bank digital-word of data-converters, wherein thedata-converter's whole digital word is comprised of the LSB bankdigital-word plus the MSB bank digital-word.

The term non-linear data-converter (DAC or ADC) refers to adata-converter whose transfer function (as arranged by thedata-converter's reference network) is non-linearly weighted (e.g.,square or logarithmic or individually weighted). Similarly, the termlinear data-converter (DAC or ADC) refers to a data-converter whosetransfer function (as arranged by the data-converter's referencenetwork) is linearly weighted (e.g., binary or equally weightedthermometer).

Throughout this disclosure, for demonstrative and descriptive clarity,data-converter that may be illustrated with 2 to 8 bits of resolution,but they can be arranged with higher resolutions, unless otherwisespecified (e.g., disclosed data-converters can have higher resolutionswhere 16-bits of resolution is practical). Moreover, for descriptiveclarity illustrations are simplified, where their modifications forimprovements would be obvious to one skilled in the arts, such as forexample cascading current sources by stacking MOSFETs to increase theiroutput impedance. In some instances, analog switches are shown as singleFETs with one input, one output, and a control input. In such instances,the one FET acting as a switch can be replaced with two FETs with acommon input but opposite control polarity to manage the switch input'son and off voltage span and improve on-off glitch transients.

Consider that other manufacturing technologies, such as Bipolar, BiCMOS,and others can utilize the disclosure in whole or part.

Unless otherwise specified, the illustrated data-converters aregenerally asynchronous (i.e., they are clock free) which eliminates theneed for a free running clock and improves dynamic power consumptionwith lower clock noise. However, the methods, systems, or circuitsdisclosed generally are applicable to data-converters that aresynchronous (i.e., requiring clocks).

This disclosure presents several SPICE circuit simulations showing thevarious waveforms attributed to the disclosed data-converts andmultipliers. The simulations are performed in order to demonstratefunctionality of the disclosed embodiments. These simulations are notintended to guarantee the embodiment's performance to a particular rangeof specifications. Be mindful that circuit simulations use the TOPSPICEsimulator, and are based on approximate device models for a typicalstandard mainstream 0.18 μm CMOS process fabrication.

Throughout this disclosure, data-converters utilized in multipliers andmultiply-accumulate circuits operate in current-mode and generally havethe following benefits:

First, data-converters operating in current-mode are inherently fast.

Second, current signal processing that occurs within the nodes ofdata-converters, generally, have small voltage swings which enablesoperating the current-mode data-converters with lower power supplyvoltages.

Third, operating at low supply voltage reduces power consumption ofcurrent-mode data-converters.

Fourth, current input and current output zero-scale to full-scale spansof current-mode data-converters are less restricted by power supplyvoltage levels (e.g., current input and outputs can generally span tofull-scale at minimum power supply voltages)

Fifth, current mode CMOS data-converters can operate in subthresholdthat enables reducing power consumption further.

Sixth, summation and subtraction functions in analog current-mode isgenerally simple and takes small chip area. For example, summation oftwo analog currents could be accomplished by coupling the currentsignals. Depending on accuracy and speed requirements, subtraction ofanalog current signals could be accomplished by utilizing a currentmirror where the two analog current signals are applied to the oppositeside of the current mirror, for example.

Seventh, current-mode data-converters can operate internally inmixed-mode and externally have compatible interface with conventionaldigital processors. For example, digital-to-analog converters andmultipliers can operate in current mode analog and or mixed-mode andsubsequently have their current mode computations be converted todigital in order to seamlessly interface with standard digitalprocessors via current-mode analog-to-digital converters.

Eight, accuracy of mixed-signal current-mode data-converters, dependingon the architecture, generally depends (at least in part) on thematching between FET current sources in the data-converter's currentreference or bias network that programs their transfer function.Moderate conversions speeds with typical accuracies up to 16-bits withtrimming or calibration and up to 10-bits without trimming orcalibration may be achievable in standard CMOS manufacturing, wherenon-minimum size FETs are utilized to form the data-converter's currentreference or bias network. Such accuracies can be sufficient for a rangeof near-edge or near-sensor machine learning and artificial intelligence(ML & AI) applications that may also not require extremely fastcomputation speeds. As such, some near-edge or near-sensor ML & AIapplications can benefit from the low-cost and low-power of mixed-signalcurrent-mode computation that only requires low cost conventional CMOSmanufacturing, as compared to high-speed power-hungry high-precisiondigital processors that require the substantially more expensivedeep-sub-micron CMOS technologies.

Section 1—Description of FIG. 1

FIG. 1 is a simplified block diagram illustrating a floatingcurrent-mode (i) digital-to-analog-converter (iDAC) method.

The disclosed floating iDAC method, substantially equalizes a referencecurrent signal (I1 ₁) with the sum of a plurality of currents that aregenerated by plurality of floating voltage controlled current sources(VCCS). The plurality of VCCS's currents are scaled by programming eachof the VCCS's voltage-to-current transconductance gains (G). Moreover,the plurality of VCCS's currents are selected by a plurality ofrespective current switches (iSWs) wherein the iSWs are controlled bythe iDAC's digital input word, to steer the iSW's respective outputs toiDAC's outputs (I_(O) ⁺ and I_(O) ⁻).

The floating iDAC method can be utilized in an iDAC having a n-bit(n≤16) wide digital word (Di₁), a current reference signal (I1 ₁), andtwo analog current outputs such as a first analog current outputterminal Io₁ ⁺ and a second analog current output terminal Io₁ ⁻(coupled with a bias voltage source such as V1 ₁). The floating iDACmethod is illustrated in a system diagram of FIG. 1 having plurality(e.g., n=3) of VCCSs or voltage controlled current sources (e.g., G1 ₁,G2 ₁, and G3 ₁). Each VCCS has a positive input voltage terminal and anegative input voltage terminal (VCCS_(V) ⁺, and VCCS_(V) ⁻) and apositive output current terminal and a negative output current terminal(VCCS_(I) ⁺, and VCCS_(I) ⁻). The respective VCCS's output currents(e.g., I_(G3) ₁ , I_(G2) ₁ , and I_(G1) ₁ ) flow-in is the respectiveVCCS's positive current output terminals VCCSs and flow-out of therespective VCCS's negative current output terminals VCCS_(I) ⁻s. At nodeng 1, the floating iDAC method receives a reference current signal I1 ₁.Each of the negative input voltage terminals of the plurality of VCCSs,and each of the negative output current terminals of plurality of VCCSsare coupled together at node ng 1. Each of the positive input voltageterminal of the plurality of VCCSs are coupled together that is alsocoupled with a voltage signal from a voltage source V2 ₁. Consider that,I_(G3) ₁ , I_(G2) ₁ , and I_(G1) ₁ current sources are floating on I1 ₁which is a floating iDAC's reference current source. There is aplurality of current switches (iSW) each with a digital control input,an analog current input, and two analog current output terminals. Therespective digital control inputs of the plurality of iSWs are coupledwith the respective plurality of iDAC's digital input bits (that make upthe digital word Di_(i)). When the iSW's digital control input isenabled (e.g., positive polarity), then the iSW's analog input currentis routed to Io₁ ⁺ which a first analog current output of iDAC. When theiSW's digital control input is disabled (e.g., negative polarity), thenthe iSW's analog current input is routed to the second analog currentoutput of iDAC or Io₁ ⁻.

In illustration of FIG. 1, given V2 ₁−V_(ng) ₁ =V_(f1), then I_(G1) ₁=V_(f1)×S₁×g, I_(G2) ₁ =V_(f1)×S₂×g, and I_(G3) ₁ =V_(f1)×S₃×g. As notedearlier, the plurality of output currents (e.g., I_(G1) ₁ , I_(G2) ₁ ,and I_(G3) ₁ ) of the respective the VCCSs (e.g., G1 ₁, G2 ₁, and G3 ₁,respectively) are fed onto the respective plurality of iSW's inputs.Accordingly, I_(G1) ₁ +I_(G2) ₁ +I_(G3) ₁ =I1 ₁=I_(R), where I_(R) isthe reference current to the iDAC and establishes the full-scale out ofthe iDAC. The V_(f1) is the voltage input to each of the VCCSs. Thetransconductance gain of a single unit VCCS is g, which is scaled byprogramming the gain scale factors (e.g., s₁, s₂, and s₃) for eachrespective VCCS.

Let's consider programming the VCCS's gain factors for a binary weightediDACs. In a general, a simplified transfer function for an iDAC is:

${I_{o} = {{I_{R}{\sum\limits_{i = 1}^{n}{D_{i}/2^{i}}}} = {{\left( {I_{R}/2^{n}} \right){\sum\limits_{i = 1}^{n}{D_{i} \times 2^{i - 1}}}} = {\Delta_{R}{\sum\limits_{i = 1}^{n}{D_{i} \times 2^{i - 1}}}}}}},$where for the iDAC, I_(o) is the analog output current, I_(R) is thereference input current that can set the full-scale value of I_(o),D_(i) is the digital input word (that is n-bits) wide, andΔ_(R)=(I_(R)/2^(n)) is the analog LSB current weight of I_(o). For aniDAC with n=3, by programming gain scale factors s₁=1, s₂=2, and s₃=4,then I_(G1) ₁ =I_(G1) ₂ /2=I_(G1) ₃ /4 which is a binary weightedcurrent source network, whose binary weighted current sources areselected by iSWs in accordance with the Di_(i) digital input word of theiDAC. Note that the iDAC's full scale is I_(R)=I1 ₁=I_(G1) ₁ +I_(G1) ₂/2+I_(G1) ₃ /4. Note also that the VCCS's gain scale factors can beprogrammed to other ratios, including but not limited to, substantiallyequal ratio (which enables making a thermometer coded current-mode DAC),or non-linear ratio (which enables making for example a logarithmiccurrent-mode DAC or a current-mode DAC with a square transfer fiction).Some of the benefits of the floating iDAC method is highlighted in itsembodiment disclosed in FIG. 2 section 2 next.

Section 2—Description of FIG. 2

FIG. 2 is a simplified circuit schematic diagram illustrating anembodiment of an iDAC that utilizes the floating iDAC method illustratedin FIG. 1.

As noted earlier, for illustrated clarity, a n=3 bits binary weightediDAC is described but n can be as large of 16 bits. Bias voltage V2 ₂provides the positive input voltage to the gate terminal of 3field-effect-transistors (FETs) M4 ₂, M5 ₂, and M6 ₂, which perform thefunction of the three VCCSs (corresponding to G1 ₁, G2 ₁, and G3 ₁functions in FIG. 1, respectively) as floating current sources. By thescaling width over length ratios (W/L) of M4 ₂, M5 ₂, and M6 ₂, therespective plurality of VCCS's transconductance gain factors can beprogrammed. Bear in mind that, I_(M4) ₂ , I_(M5) ₂ , and I_(M6) ₂ may bedescribed as floating current sources on I_(M2) ₂ . For nomenclatureclarity consider that, as an example, I_(M2) ₂ refers to thedrain-to-source current of MOSFET M2 ₂, which is a manner of terminologyis applied throughout out this disclosure. In a binary weighted iDAC,the gain factors s₁=1, s₂=2, and s₃=4, and as a result I_(M6) ₂ =I_(M5)₂ /2=I_(M4) ₂ /4. Consider that s₄ scale ratio of M3 ₂ is not criticaland can be programmed to, for example, 1 in the binary weighted iDACcase, so long as the drain-to-source voltage (V_(DS)) of M1 ₂ and M2 ₂are matched close enough to keep the FET's early voltage (V_(A))mismatch error within design objectives. By operation of the Kirchhoff scurrent law (KCL) at node ng₂, I_(M6) ₂ +I_(M5) ₂ +I_(M4) ₂ =I_(M2) ₂ ,which substantially equalizes the full-scale current of the iDAC toI_(M2) ₂ =I_(R′) (notice that I_(M2) ₂ of FIG. 2 is analogous toequivalent of I_(R)=I1 ₁ of FIG. 1). The iDAC's digital-input words,from Most-Significant-Bit (MSB) D3 ₂ to Least-Significant-Bit (LSB) D1 ₂control the respective iDAC's iSWs: M7 ₂-M8 ₂, M9 ₂-M10 ₂, and M11 ₂-M12₂. For example, when D3 ₂ is in high state (i.e., MSB is on), then theiSW M8 ₂ is on and iSW M7 ₂ is off and accordingly I_(M4) ₂ is steeredthrough M8 ₂ to the iDAC's current output port Io_(2f+). If D3 ₂ is inlow state, then M4 ₂'s current is steered through M7 ₂ to the iDAC'ssecond current output port Joy. Similarly, and in accordance with thepolarity of the iDAC's digital input words, the iSWs steer therespective iDAC's binary weighted currents I_(M4) ₂ , I_(M5) ₂ , andI_(M6) ₂ onto either the Io₂ ⁺ port (which is the iDAC's first analogcurrent output port) or the second iDAC analog current output port Io₂ ⁻(that is in this case shunted onto voltage source V1 ₂).

For illustrative clarity, programming current mirror scale factor a=b=1,then I1 ₂=I_(M1) ₂ =I_(M2) ₂ =I_(R′). The injection currents I2 ₂=I3 ₂are applied to both side of M1 ₂-M2 ₂ current mirror to prevent the saidmirror from shutting off, thus improving its dynamic response, when I1 ₂is pulsed between zero and full scale. Also, consider that by utilizingthe floating iDAC method, the scaling of iDAC reference current network(e.g., M4 ₂, M5 ₂, and M6 ₂) are decoupled from the scaling of I1 ₂through M1 ₂-M2 ₂ mirror W/L ratios. Such decoupling of currentreference network scaling, reduces FET's sizes and lowers thecapacitance associated with the small scaled FETs which also improvesthe iDAC's transient response and lowers glitch.

Note that the floating iDAC disclosed in FIG. 2 generally utilizesNMOSFETs, including for iSWs and for the floating current sourcetransfer function network. Variations of this disclosure would beobvious to one skilled in the art, including to utilize a complementaryfloating iDAC comprising of NMOS current reference sources and PMOSiSWs, or combination thereof.

In summary, some of the benefits of the floating iDAC method disclosedin section 1 FIG. 1, and such benefits flowing into the embodiment ofthe floating iDAC of FIG. 2, which are as follows:

First, the floating VCCSs generate the scaled current reference networkfor the iDAC, that can be decoupled from the scaling of I_(M1) ₂ ,I_(M2) ₂ mirror and I1 ₂ reference current. The decoupling of scaling ofcurrent reference network provides a degree of freedom that helps theiDAC reduce FET scaling and sizes which saves die are, lowers cost, andalso lowers the capacitance attributed to larger size FETs in the iDAC'scurrent reference network which in turn improve the transient responseof the iDAC.

The decoupling of scaling of current reference network, also providessimple means to improve the dynamic response of the iDAC when itsreference input signal I1 ₂ is pulsed between zero and full scales. Thisis accomplished by injecting currents b×I2 ₂=a×I3 ₂ to both side of M1₂-M2 ₂ current mirror to prevent the mirror from shutting off, and henceimproving its dynamic response.

Second, the iDAC operating in current-mode is inherently fast.

Third, voltage swings in current-mode signal processing are small, whichenables operating the iDAC with lower power supply voltage and retainthe speed and dynamic rage benefits. Also, floating iDAC can operatewith low power supplies since its operating headroom can be limited by aFET's VGS+VDS. Additionally, the flexibility to run the CMOSFETs insubthreshold enables a floating iDAC to operate with ultra-low currents,even lower power supplies, and ultra-low power consumption suitable formobile applications, especially in AI and ML applications that mayrequire numerous ultra-low power and low power supply DACs forcomputation.

Fourth, operating at low supply voltage reduces power consumption.

Fifth, signal processing such as addition or subtraction, in currentmode, are also small and fast.

Sixth, the VCCS's gain factor can be programmed for an objective iDAC'stransfer function such as binary weighted, thermometer, logarithmic,square function, or other non-linear iDAC transfer functions, asrequired by the application.

Seventh, by substantially equalizing the terminal voltages at Io₂ ⁺ andIo₂ ⁻ (e.g., to V1 ₂), the iSW's transient and glitch responses areimproved since the two outputs of iSW at Io₂ ⁺ and Io₂ ⁻, could swingbetween approximately equal voltages, during on and off iDAC's digitalinput code transitions.

Eight, there are no passive devices in the embodiment of FIG. 2, and assuch there is no need for resistors or capacitors, which reduces diesize and manufacturing cost. Not requiring any capacitors nor anyresistors would facilitates fabricating a floating iDAC in standarddigital CMOS manufacturing that is not only low cost, but alsomain-stream and readily available for high-volume mass productionapplications, and proven for being rugged and having high quality.

Ninth, the precision of the iDAC can be improved by for exampleutilizing current source segmentation (along with digitalbinary-to-thermometer logic decoding of iDAC's digital input code), orcascading the iDAC's reference current mirrors to improve their outputimpedance.

Tenth, a floating iDAC can be arranged free of clock, suitable forasynchronous (clock free) computation.

Eleventh, a floating iDAC can utilize same type of MOSFET currentsources and MOSFET switches that are arranged in a symmetric, matched,and scaled manner. This trait facilitates devices parameters to trackeach other over process, temperature, operating condition variations.Accordingly, the iDAC's temperature coefficient, power supplycoefficient, and AC power supply rejection performance can be enhanced.

Twelfth, the embodiment disclosed here is not restricted by FETs havingto operate either in saturation (high-currents) or subthreshold (lowcurrents) regions. For example, some analog signal processing units relyon operating transistors in the subthreshold regions which restricts thedynamic range of analog signal processing circuits to low currentsignals. Also, some other analog signal processing units rely onoperating transistors with high currents in the saturation regions whichrestricts the dynamic range of analog signal processing circuits tohigher current signals.

Section 3—Description of FIG. 3

FIG. 3 is a simplified circuit schematic diagram illustrating anembodiment of an iDAC that combines a plurality of iDACs to arrange ahigher resolution iDAC, wherein at least one of the plurality of iDACsutilizes the floating iDAC method illustrated in FIG. 1.

The individual floating iDACs utilized in FIG. 3 are arranged in asimilar manner as that of FIG. 2 in section 2. FIG. 3 illustrates a5-bit iDAC but higher resolutions iDACs can be arranged and up to16-bits of resolution is practical. The ID AC of FIG. 3 is comprising ofa first 2-bits floating iDAC that is a most-significant bank (MS bankiDAC) and a second 3-bits floating iDAC that is a least-significant bank(LS bank iDAC). Here, the full-scale output current weight of the MSbank iDAC is 2²=4 times bigger than that of the LS bank iDAC. The MSB ofthe 5-bit iDAC is D5 ₃ and the LSB of the 5-bit iDAC is D1 ₃. The 5-bitiDAC's reference current in FIG. 3 is I1 ₃ and the iDAC's outputcurrents are Io₃ ⁺ and Io₃ ⁻.

The upper half of FIG. 3 (that is outside the Block 3A dotted area) isthe LS bank iDAC (with D1 ₃, D2 ₃, and D3 ₃ as its respective digitalinputs) that is similar to that of FIG. 2 described in section 2. Thelower half of FIG. 3 that is inside the Block 3A dotted area is a 2-bitfloating iDAC which is the MS bank iDAC (with D4 ₃, and D5 ₃ as itsrespective digital input bits) generating a positive and a negativeoutput currents Im₃ ⁺ and Im₃ ⁻ (respectively) that are added to(coupled with) the iDAC's output currents to produce the total Io₃ ⁺ andIo₃ ⁻.

To optimize for cost-performance objective, the embodiment illustratedin FIG. 3 has the flexibility to program the reference current value andiDAC's input-to-output transfer function. For descriptive clarity of theoperations of FIG. 3, let's program the 5-bit iDAC as binary weighted(instead of a non-linear or thermometer input-out transfer function forthe iDAC, for example). As an example, with the reference current I1₃=8I_(R), let's program the reference current mirror scale factors inthe iDAC's transfer function network as follow: M13 ₃'s c=3, M2 ₃'s b=1,and M1 ₃'s a=1. Also, let's program s₆=2×s₅ and analogous to the examplein section 2 (pertaining to FIG. 2) s₃=2×s₂=4×s₁. Notice that, I_(M14) ₃and I_(M15) ₃ can be viewed as floating current sources on I_(M13) ₃ .Similarly, I_(M4) ₃ , I_(M5) ₃ , I_(M6) ₃ , and I_(M20) ₃ can be viewedas floating current sources on I_(M23). With scale factors programmed asnoted above, a binary weighted current reference network can be arrangedas follows: I_(M13) ₃ =24I_(R)→I_(M14) ₃ =16I_(R), I_(M15) ₃ =8I_(R) forthe MS bank iDAC. Also, I_(M1) ₃ =I_(M2) ₃ =8I_(R)→I_(M4) ₃ =4I_(R),I_(M5) ₃ =2I_(R), and I_(M6) ₃ =I_(R) for the LS bank iDAC. Considerthat with I_(M2) ₃ =8I_(R) and M20 ₃'s S₁=1, then I_(M20) ₃ =I_(R) whichleaves 7I_(R) to be split in accordance with programmed scaled factorss₃=2×s₂=4×s₁ between I_(M4) ₃ =4I_(R), I_(M5) ₃ =2I_(R), and I_(M6) ₃=I_(R).

Additionally, bear in mind that I_(M20) ₃ =I_(R) is terminated in Io₃ ⁻in this example, but I_(M20) ₃ can be terminated in Io₃ ⁺ depending onzero-scale or full scale (LSB current) offset requirement of theend-application. Moreover, note that the same voltage source V2 ₃ biasesthe gate terminals of M14 ₃, M15 ₃, and M20 ₃. As means for improvingthe transient recovery time of M1 ₃, if and when I1 ₃=8I_(R) is pulsedbetween zero and full scale, a proportional constant current (Ij₃ whichis not shown but) can be added onto I1 ₃, to keep M1 ₃ alive, plus twoscaled Ij₃ can be injected into nodes ng₃ and ng_(3′). Also considerthat similar to FIG. 2 in section 2, the purpose of utilizing V1 ₃ inFIG. 3 is to substantially equalize the Io₃ ⁺ and Io₃ ⁻ terminalvoltages for better matching and dynamic response (e.g., if Io₃ ⁺ isterminated into a diode connected current mirror, then V_(GS) of a diodeconnected FET can also be utilized to set the V1 ₃ for Io₃ ⁻).

Notice that the floating iDAC disclosed in FIG. 3 generally utilizesNMOSFETs, including for iSWs and the floating current source transferfunction network. It would be obvious to one skilled in the art toutilize a complementary floating iDAC comprising of PMOS or acombination of PMOS and NMOS current reference transfer function andPMOS iSWs.

In addition to some of the benefits of the floating iDAC methoddisclosed in section 2 FIG. 2, the embodiment of FIG. 3 illustrates thatthe floating iADC method is scalable and can be expanded in combinationwith other iDACs to attain higher resolutions.

Section 4—Description of FIG. 4

FIG. 4 is a simplified circuit schematic diagram illustrating anotherembodiment of an iDAC that combines a plurality of iDACs to arrange ahigher resolution iDAC, wherein at least one of the plurality of iDACsutilizes the floating iDAC method illustrated in FIG. 1.

The iDAC illustrated in FIG. 4 is similar to the iDAC described in FIG.3 section 3 with the difference being the MS bank iDAC is not a floatingiDAC. FIG. 4 illustrates a 5-bit iDAC but higher resolutions iDACs canbe arranged and up to 16-bits of resolution is practical. The iDAC ofFIG. 4 is comprising of a first 2-bits iDAC that is a most significantbank (MS bank iDAC shown inside the dotted line as Block 4A). The iDACof FIG. 4 is also comprising of a second 3-bits floating iDAC that is aleast significant bank (LS bank iDAC). In iDAC of FIG. 4 the full-scaleoutput current weight of the MS bank iDAC is 2²=4 times bigger than thatof the LS bank iDAC. The MSB of the 5-bit iDAC in FIG. 4 is D5 ₄ and theLSB of the 5-bit iDAC is D1 ₄. The 5-bit iDAC's reference current inFIG. 4 is I1 ₄ and the iDAC's output currents are Io₄ ⁺ and Io₄ ⁻.

The upper half of FIG. 4 (that is outside the Block 4A dotted area) isthe LS bank iDAC (with D1 ₄, D2 ₄, and D3 ₄ as its respective digitalinputs) similar to that of FIG. 2 and FIG. 3 that were described insections 2 and 3, respectively. As noted earlier, the lower half of FIG.4 that is inside the Block 4A dotted area is another 2-bit floating iDACwhich is the MS bank iDAC (with D4 ₄, and D5 ₄ as its respective digitalinputs) generating a positive and a negative output currents Im₄ ⁺ andIm₄ ⁻ (respectively) which are added to (by being coupled with) thefirst iDAC's output currents Io₄ ⁺ and Io₄ ⁻.

To optimize for cost-performance objective, there is flexibility inprogramming the iDAC's reference current value and input-output transferfunction network of the iDAC in FIG. 4. To describe the operations ofFIG. 4, let's program the 5-bit iDAC as binary weighted for the purposeof the disclosure's descriptive clarity. As an example, with thereference current I1 ₄=8I_(R), let's program the reference currentmirror W/L scales as follow: M13 ₄'s c=2, M20 ₄'s d=1, M2 ₄'s b=1, andM1 ₄'s a=1. Let's program S₃=2×S₂=4×S₁ in FIG. 4. With W/L scalesprogrammed as such, a binary weighted current reference network isarranged comprising of I_(M13) ₄ =16I_(R), I_(M20) ₄ =8I_(R) for the MSbank iDAC. As noted earlier, I_(M4) ₄ , I_(M5) ₄ , I_(M6) ₄ , andI_(M21) ₄ current sources can be viewed as floating on I_(M2) ₄ . Also,I_(M1) ₄ =I_(M2) ₄ =8I_(R)→I_(M4) ₄ =4I_(R), I_(M5) ₄ =2I_(R), andI_(M6) ₄ =I_(R) for the LS bank iDAC in FIG. 4. Given that I_(M2) ₄=8I_(R) and M21 ₄'s S₁=1, then I_(M21) ₄ =I_(R) which leaves 7I_(R) tobe split in accordance with programmed scaled factors S₃=2×S₂=4×S₁between I_(M4) ₄ =4I_(R), I_(M5) ₄ =2I_(R), and I_(M6) ₄ =I_(R).

Additionally, consider that in FIG. 4, I_(M21) ₄ =I_(R) is terminated inIo₄ ⁻ in this example, but I_(M21) ₄ can be terminated in Io₄ ⁺depending on zero-scale or full scale (LSB current) offset requirementof the application. Moreover, consider that the same voltage source V2 ₄biases the gate terminals of M14 ₄, M15 ₄, and M20 ₄. As means forimproving the transient recovery time of M1 ₄, when I1 ₄=8I_(R) ispulsed between full and zero scales, a proportional constant injectionDC current (Ij₄ which is not shown but) can be added onto I1 ₄, to keepM1 ₄ alive, plus two scaled Ij₄ can be injected into nodes ng₄ and thedrain terminals of FETs M13 ₄ and M20 ₄. Also bear in mind that similarto FIG. 2 in section 2, the purpose of utilizing V1 ₄ in FIG. 4 is tosubstantially equalize the Io₄ ⁺ and Io₄ ⁻ terminal voltages for bettermatching and dynamic response (e.g., if Io₄ ⁺ is terminated into a diodeconnected current mirror, then V_(GS) of a diode connected FET can alsobe utilized as the V1 ₄ for Io₄ ⁻).

In addition to some of the benefits of the floating iDAC methoddisclosed in section 2 FIG. 2, the embodiment of FIG. 4 illustrates thatthe floating iADC method is scalable and can be expanded throughcombination with other iDACs to attain higher resolutions.

Section 5—Description of FIG. 5

FIG. 5 is a simplified schematic diagram illustrating a mixed-signalcurrent-mode digital-input to analog-current-output multiplier(XD_(i)I_(o)) comprising of a first iDAC whose output supplies thereference input to a second iDAC, wherein the first and second iDACsutilize the floating iDAC method illustrated in FIG. 1

The first and second floating iDACs embodiments are similar to thefloating iDAC described and illustrated in section 2 FIG. 2.

For clarity of description, both floating iDACs of FIG. 5 are arrangedas binary-weighted, and accordingly the current referencetransfer-function is programmed for FET W/L scales s₃=2×s₂=4×s₁.

For illustrative clarity, instead of showing iSWs with FET level circuitschematics (e.g., FIG. 2 section 2 where MSB current switch comprisingM7 ₂, U1 ₂, and M8 ₂ etc.), the iSWs in FIG. 5 are shown as blockdiagrams (e.g., MSB current switch S1 ₅, etc.) utilized in floatingiDACs. Additionally, bear in mind that the XD_(i)I_(o) illustrates a3-bit digital input word Q being multiplied with a 3-bit digital word P,but each P and Q digital input words can be up to 16-bits.

The left side of FIG. 5 illustrates the first floating iDAC (Q-iDAC)with its Q_(D) digital-input word (comprising of 3-bits Q1 ₅, Q2 ₅, andQ3 ₅ where Q1 ₅ is the MSB and Q3 ₅ is the LSB), and its reference inputcurrent I_(R)=I1 ₅. The I1 ₅ is fed onto a diode connected FET M1 ₅whose current is scaled and mirrored onto M2 ₅ in accordance with theprogrammed W/L scales a and b of M1 ₅ and M2 ₅, respectively. Forclarity of this description, let's set a=b=1, and thus I_(R)=I1₅=I_(M15)=I_(M25).

The Q-iDAC's positive and negative analog output currents Iq₅ ⁺ and Iq₅⁻ are generated as a function of its Q digital-input word and I1 ₅. Thedigital-input to analog-current-output transfer-function of the Q-iDAC,which is binary weighted in FIG. 5's illustration, can mathematically beexpressed as

${Iq}_{5}^{+} = {{\left( {I_{R}/2^{n}} \right) \times {\sum\limits_{i = 1}^{n}{Q_{i_{5}} \times 2^{i - 1}}}} = {\Delta_{R} \times {\sum\limits_{i = 1}^{n}{Q_{i_{5}} \times {2^{i - 1}.}}}}}$Here, for a=b=1, Iq₅ ⁺=I_(M8) ₅ =I_(M9) ₅ is the analog-output currentof the Q-floating iDAC. Also, Δ_(R)=I_(R)/2^(n)) with I_(R)=I1 ₅, andn=3 is the resolution of the Q-floating iDAC. Lastly, Q_(i) ₅ is 0 or 1representing the value of the i^(th) digital input bits (with 3-bits Q1₅, Q2 ₅, and Q3 ₅) of the Q-floating iDAC. Let's simplify the Q-floatingtransfer function representation as Iq₅ ⁺=I1 ₅×f(Q_(D)). Consider thatthe Iq₅ ⁺ is fed onto a diode-connected FET M8 ₅ whose current is scaledand mirrored onto M9 ₅ to supply the reference current signal for theP-iDAC.

The right side of FIG. 5 illustrates the P-iDAC with its P_(D)digital-input word (comprising 3-bits P1 ₅, P2 ₅, and P3 ₅ where P1 ₅ isthe MSB and P3 ₅ is the LSB) and its reference input current I_(M8) ₅=Iq₅ ⁺=I1 ₅×f(Q_(D))=I_(M9) ₅ considering the programmed W/L scalesarrangement where a=b=1. Consider that in FIG. 5's illustration, theiSWs in P-iDACs are PMOSFETs whereas the iSWs in Q-iDACs are NMOSFETs.Accordingly, the Q_(D) and P_(D) digital-input words are properlyarranged to apply the complementary digital-input signs to the FIG. 5'siSW s.

The P-iDAC's positive and negative analog output currents Ipq₅ ⁺ andIpq₅ ⁻ are generated as a function of its P-digital-word and I_(M9) ₅ .The digital-input to current analog-output transfer-function of theP-iDAC (that is binary weighted in the illustration of FIG. 5) can alsomathematically be expressed as:

${Ipq}_{5}^{+} = {{\left( {I_{R^{\prime}}/2^{m}} \right) \times {\sum\limits_{j = 1}^{m}{P_{j_{5}} \times 2^{j - 1}}}} = {{\Delta_{R^{\prime}} \times {\sum\limits_{j = 1}^{m}{P_{j_{5}} \times 2^{j - 1}}}} = {{I_{M9_{5}}/2^{m}} \times {\sum\limits_{j = 1}^{m}{P_{j_{5}} \times 2^{j - 1}}}}}}$where Ipq₅ ⁺ is the positive analog output current of the P-iDAC, I_(M9)₅ =I_(q) _(5=I1) ₅×f(Q_(D)), and m=3 is the resolution of the P-iDAC andP_(j) ₅ is 0 or 1 representing the value of the j^(th) digital inputbits (with 3-bits P1 ₅, P2 ₅, and P3 ₅) of the P-iDAC. Therefore, theP-iDAC transfer function can be represented in the simplified form: Ipq₅⁺=I1 ₅×f(Q_(D))×f(P_(D)) or f(Q_(D))×f(P_(D))=I_(pq) ₅ /I1 ₅ which is anexpression that represents the multiplication results of twodigital-input words Q_(D) and P_(D), where the multiplication result isrepresented as an analog-output current I_(pq) ₅ proportional to acurrent proportional to I1 ₅ which is proportional to a referencecurrent (I_(R)).

Bear in mind that the Ipq₅ ⁻ is fed onto a voltage source V2 ₅ to matchterminal voltage at Ipq₅ ⁺. Furthermore, as means to enhance the dynamicresponse of reference mirror current signals that is subjected to apulse, I2 ₅ is added as a constant current injection (Ij₅) to keep M8 ₅alive when for example Ipq₅ ⁺ transitions between zero and full scale.As such, a proportional I3 ₅ is added to M9 ₅ to balance the currentmirror M8 ₅-M9 ₅.

In summary some of the benefits of the XD_(i)I_(o) utilizing thefloating iDAC method are as follows:

First, the decoupling of scaling of current reference network, helpsreduce FET sizes which saves die are, lowers cost. This trait alsolowers the capacitance attributed to large size FETs in the iDAC'scurrent reference network, which in turn improves the transient responseof the floating iDAC and the multiplier XD_(i)I_(o) that utilizes suchiDACs. The decoupling of scaling of current reference network, alsoprovides simple means to improve the dynamic response of the iDAC andthat of the multiplier XD_(i)I_(o) when the iDAC's reference inputsignal is pulsed. One mean of accomplishing this goal is by injecting ascaled DC current on each side of the current mirror that supplies theiDAC's reference current, which helps prevent the mirror from shuttingoff, and thus improving its dynamic response.

Second, the XD_(i)I_(o) operating in current-mode is inherently fast.

Third, voltage swings in current-mode signal processing are small, whichenables operating the XD_(i)I_(o) with lower power supply voltage.

Fourth, operating at low supply voltage reduces power consumption of theXD_(i)I_(o). Additionally, the flexibility to run the CMOSFETs insubthreshold enables the iDAC to operate with ultra-low currents, evenlower power supplies, and ultra-low power consumption suitable formobile applications, especially in AI and ML applications that mayrequire numerous ultra-low power and low power supply DACs forcomputation.

Fifth, XD_(i)I_(o)'s output signal processing in current-mode such asaddition or subtraction functions are also small and fast, which forexample is important in ML & AI applications requiring plurality ofmultiplier's outputs to be (summed) accumulated. For example, to sumplurality of signals in current-mode simply involves coupling thecurrent signals together.

Sixth, by substantially equalizing the terminal voltages at the positiveand negative current output of the iDAC, it would improve the iSW'stransient response and reduces glitch between the iSW's on to offtransitions, which helps the transient response of the XD_(i)I_(o).

Seventh, there are no passive devices in the embodiment of FIG. 5, andas such there is no need for resistors or capacitors, which reducesmanufacturing size and cost of the XD_(i)I_(o).

Eighth, the precision of the iDAC and hence the precision of theXD_(i)I_(o) multiplier can be improved by for example utilizing currentsource segmentation (along with digital binary-to-thermometer coding) inthe iDAC's reference current transfer-function, or cascading the iDAC'sreference current mirrors to improve their output impedance.

Ninth, utilizing lower resolution iDACs (e.g., 3-bits or 5-bits) in theXD_(i)I_(o) multiplier, that occupy smaller areas, but have higheraccuracy (e.g., 8-bits of resolution corresponding to accuracy of ±0.4%)is beneficial. For example, higher than 3 of 5 bits of accuracy isattainable in standard CMOS fabrication. With proper W/L scaling of FETsused in the current source transfer function of iDACs, 8-bits ofaccuracy or ±0.4% matching may be achievable. As such, this disclosurecan utilize low resolution iDACs that occupy small areas and achievehigher accuracy P_(A)×Q_(A) multiplication at lower cost.

Tenth, the XD_(i)I_(o) that utilizes floating iDAC can be arranged freeof clock, suitable for asynchronous (clock free) computation.

Eleventh, the XD_(i)I_(o) that utilizes same type of MOSFET currentsources and MOSFET switches in the respective floating iDACs, which aresymmetric, matched, and scaled. This trait facilitates devicesparameters to track each other over process, temperature, and operatingconditions variations. Accordingly, the XD_(i)I_(o)'s temperaturecoefficient, power supply coefficient, and AC power supply rejectionperformance can be enhanced.

Twelfth, the embodiment disclosed here is not restricted by FETs havingto operate either in saturation (high-currents) or subthreshold (lowcurrents) regions. For example, some analog signal processing units relyon operating transistors in the subthreshold regions which restricts thedynamic range of analog signal processing circuits to low currentsignals. Also, some other analog signal processing units rely onoperating transistors with high currents in the saturation regions whichrestricts the dynamic range of analog signal processing circuits tohigher current signals

Section 6—Description of FIG. 6

FIG. 6 is a simplified circuit schematic diagram illustrating anotherembodiment of an iDAC that utilizes the floating iDAC method illustratedin FIG. 1.

The embodiment of floating iDAC illustrated in FIG. 6 is similar to thatof the floating iDAC embodiment disclosed and illustrated in section 2and FIG. 2. The difference is a smaller iSW arrangement which simplifiesthe iDAC, reduces its size, and lowers its dynamic power consumption.Small size of iDAC is critical in machine learning and artificialintelligence applications that could require numerous iDACs formultiplication purposes. The iSW here is, for example, comprising of M8₆ and M7 ₆, where in M8 ₆ receives the digital bit D3 ₆ whereas M7 ₆'sgate terminal is biased at a fixed V1 ₆+V3 ₆. As such, the inverter(compared to, for example, U1 ₂ in FIG. 2. Section 2) is eliminatedwhich saves are and lowers transient power consumption whendigital-inputs are updated. Note that, in this example, V1 ₆+V3 ₆ can beprogrammed such that digital voltage swings at D3 ₆ terminal properlyturn M8 ₆ on and off when D3 ₆ bit toggles. Also, depending oncost-performance goals, M13 ₆, M3 ₆, and M1 ₆ as well as the iSW's FETpairs (e.g., M7 ₆-M8 ₆, M9 ₆-M10 ₆, and M11 ₆-M12 ₆) can be sized tooptimize for FETs to operate at or near saturation with increased outputimpedance, which could improve performance of the current referencetransfer function network.

In addition to some of the benefits of the floating iDAC methoddisclosed in section 2 FIG. 2, the embodiment of FIG. 6 illustratesanother embodiment of floating iDAC with smaller size and lower dynamicpower consumption.

Section 7—Description of FIG. 7

FIG. 7 is a simplified functional block diagram illustrating afactorized iDAC method.

As noted earlier, a DAC's input-to-output transfer function can bedescribed as follow:

${A_{o} = {\left( {A_{r}/2^{i}} \right) \times {\sum\limits_{i = 1}^{n}\left\lbrack {D_{i} \times 2^{i - 1}} \right\rbrack}}},$where A_(o) is the DAC's analog output signal, A_(r) is the DAC's analogreference signal, D_(i) is the DAC's digital inputs signal that aren-bits wide. For example, for n=6, and A_(r)=1 units which establishesA_(o)'s full scale value of 1 unit. For a ½ unit or half-scale of a6-bit wide digital word corresponds to D_(i)=100000 or D₆=1, andD₅=D₄=D₃=D₂=D₁=0, the DAC's input-to-output transfer function would beas follows:A_(o)=(A_(r)/2⁶)×[D₁×2⁰+D₂×2¹+D₃×2²+D₄×2³+D₅×2⁴+D₆×2⁵]=(A_(r)/2⁶)×[0×2⁰+0×2¹+0×2²+0×2³+0×2⁴+1×2⁵]=(A_(r)/2⁶)×[1×2⁵]=A_(r)/2=½ full-scale.

Notice that the term (A_(r)/2⁶) carries the analog equivalent weight ofa least significant bit (LSB) or A_(LSB), which is binarily weighted (upto 2^(i−1) with 1<i<n=6 where i is an integer) to generate the DAC'sA_(o) (that is proportional to the DAC's A_(r) and) in accordance withthe DAC's D_(i). Here, let 2^(i−1)=2j×2^(k)=w_(i)×f_(i) where w_(i) andf_(i) represent the factors of 2^(i−1), and where there can be found apair of w_(i) and f_(i) factors whose sum is the smallest compared tow_(i)×f_(i). In other words, there can be found a pair of w_(i) andf_(i) where w_(i)+f_(i)<<w_(i)×f_(i). For example, forn=i=6→2^(i−1)=2⁵=32=2^(j)×2^(k)=2³×2²=w₆×f₆=16×2=8×4 where the sum ofthe pairs of factors here are the smallest compared to themultiplication of the pairs of factors (e.g., with j=2, k=3 or w₆=8 andf₆=4 for which 4+8<<8×4).

The factorized DAC method factorizes a respective binary DAC weights,which reduces the DAC's area and cost. The respective binary DAC weights(2^(i−1)) can be generated by feeding the respective binary DAC weight'sfactor (2^(j)=w_(i)) into its other factor (2^(k)=f_(i)) wherein2^(i−1)=2^(j)×2^(k)=w_(i)×f_(i). Utilizing the factorized DAC method,the circuit area occupied by the respective binary DAC weight's factors(2^(j)=w_(i) and 2^(k)=f_(i) in aggregate) can be optimized to occupy asmaller area compared to that of the conventional respective binary DACweights (2^(i−1)).

For example, a standard 6-bit iDAC is comprised of a plurality of binaryscaled switching current source (cells) where each current source cellcarries a current weight of A_(r)/2⁶ which is a Least-Significant-Bit orLSB. The current source cells are binarily and respectively scaled inparallel to arrange the standard iDAC's binary weighted currentswitching reference network. For example, the standard iDAC'sMost-Significant-Bit (MSB) analog current portion is generated byplacing in parallel 32 of LSB current source cells (A_(r)/2⁶) whichgenerates 32×A_(r)/2⁶=A_(r)/2. Accordingly, the MSB of a 6-bit standardiDAC's switching current sources would occupy the size of 2^(i−1)=2⁵=32of LSB switching current source cells that are arranged in parallel.

In comparison, the disclosed factorized iDAC method generates the same32×A_(r)/2⁶=A_(r)/2 or the MSB analog current portion with more areaefficiently. The factorized iDAC method, feeds the output current of2^(j)=2³=w₆=8 parallel LSB current switches (where each current switchcarries a current with the weight of an A_(LSB)) onto a current mirrorwith a gain of 2^(k)=2²=f₆=4. The current mirrors can be arranged tohave the same size as the factorized iDAC's LSB current source cells formatching purposes. As such, for the factorized iDAC method, the MSBanalog current portion of 32×A_(r)/2⁶=A_(r)/2, while occupying anequivalent aggregate current switch area of 2^(j)+2^(k)=2³+2²=8+4=12 LSBcurrent source cells. In comparison, and as noted earlier, an equivalentaggregate current source cell 2⁵=32 LSB current cells would be requiredfor a standard iDAC.

Note that there is a trade-off between reducing the area achieved byutilizing the factorized DAC method, and reducing the accuracy of theDAC. For example, the mismatch attributed to current source cells thatconstitute w₆ (subordinate DAC weight) are multiplied with the mismatchattributed to the current source cells that constitute f₆. (factorizedscale), which lowers the accuracy of the overall DAC while reducing itssize.

The area reduction benefit of the factorized DAC method can be extendedfor high resolution DACs comprising of plurality of factorized DACs. Forexample, a 6-bit DAC can be arranged by utilizing two factorized DACs(e.g., a 3-bit factorized Most-Significant-Portion of MPS DAC, and a3-bit factorized Least-Significant-Portion or LSP DAC). Alternatively, a6-bit DAC can be arranged by utilizing three factorized DACs (e.g., a2-bit factorized top portion DAC, a 2-bit factorized middle portion DAC,and a 2-bit factorized bottom portion DAC).

As noted, earlier FIG. 7 is a functional block diagram illustrating aDAC comprising of three factorized DACs, but the same factorized methodis applicable for example to 2 or 4 (instead of 3) factorized DACs.

In FIG. 7, the digital inputs Di₇ that is i₇-bit wide is applied to alogic block L₇ that arranges the digital input bits to three segments:First, a t₇-bit wide top-portion-bits or Dt₇ word. Second, a m₇-bit widemiddle-portion-bits or Dm₇ word. And third, a b₇-bit widebottom-portion-bits or Db₇ word.

In FIG. 7's illustration of factorized DAC method, the digital inputwords Dt₇, Dm₇, and Db₇ are fed onto three binary weighted subordinatedfactorized DACs: a top-DAC (DACt₇), a middle-DAC (DACm₇), and abottom-DAC (DACb₇), respectively. The three respective top, middle, andbottom DACs receive a top-analog-reference signal (tr₇), amiddle-analog-reference signal (mr₇), and a bottom-analog-referencesignal (br₇), respectively. Accordingly, the three respective top,middle, and bottom subordinated factorized DACs generate a top-weightanalog output signal (At₇), a middle-weight analog output signal (Am₇),and a bottom-weight analog output signal (Ab₇), respectively. The At₇,Am₇, and Ab₇ are then gained up by top-factor scale (Ft₇), amiddle-factor scale (Fm₇), and a bottom-factor scale (Fb₇) whoserespective output products At₇×Ft₇, Am₇×Fm₇, and Ab₇×Fb₇ are summed byan analog block A₇ to generate a final factorized DAC analog outputsignal, Ao₇. The three full-scale weights of At₇, Am₇, and Ab₇ can beprogrammed as a function of the ratio of the three reference analogsignals tr₇, mr₇, and br₇. Programming the middle-factor scale Fm₇=1 asthe base-factor, then Ft₇=2^(t) ⁷ /(tr₇/mr₇) relative to thebase-factor, and Fb₇=(½^(m) ⁷ )×(mr₇/br₇) relative to the base-factor.

Consider that for practical purposes (without any DAC calibration ortrimming): The three digital bits t₇, m₇, and b₇ can be more than 1-bitand less than 8-bit wide. The three factor scales Ft₇, Fm₇, and Fb₇ canbe programmed to gains than zero and less than 16 (without calibrationor trimming): The ratio of analog reference signals tr₇/mr₇ and mr₇/br₇can be programmed to ratios more than zero and less than 16 (withoutcalibration or trimming).

For example, let's arrange the three subordinated factorized DAC'sdigital-bits t₇=m₇=b₇=2 bits each. Let's also program the threesubordinated factorized DAC's reference analog signals substantiallyequally as tr₇=mr₇=br₇=1w. Accordingly, the three factor scales areprogrammed according to: Ft₇=2^(t) ⁷ /(tr₇/mr₇)=2²/(1)=4 and Fb₇=(½^(m)⁷ )×(mr₇/br₇)=(½²)×(1)=¼. Again, notice that the three full-scaleweights of At₇, Am₇, and Ab₇ are programmed as a function of the ratioof the three reference analog signals tr₇, mr₇, and br₇.

In an alternative example, arranging the three subordinated factorizedDAC's digital-bits t₇=m₇=b₇=2 bits each, and programming the threesubordinated factorized DAC's reference analog signals as tr₇=4w,mr₇=2w, and br₇=1w, then the three factors are programmed according to:Ft₇=2^(t) ⁷ /(tr₇/mr₇)=2²/(4w/2w)=2 and Fb₇=(½^(m) ⁷)×(mr₇/br₇)=(½²)×(2w/1w)=2.

It is of note that for a standard binary 6-bit DAC, a scale factor of2⁶⁻¹=32 LSB weights (32×) are needed to generate just the MSB signal asa multiple of the LSB weight. In comparison, for a 6-bit factorized DACthat is described in the above 2 examples, the largest scale factor is4x to generate any bit, including the MSB. In the above 2 example, thelargest scale factor is 4x in the three subordinate factorized DAC s(At₇, Am₇, and Ab₇ whose full-scale outputs are programmed with tr₇/mr₇and mr₇/br₇ ratios) as well as in the factor blocks Ft₇, Fm₇, and Fb₇.Accordingly, smaller scale factors result in smaller DAC area and aswell as other benefits such as improved dynamic response, which will bedescribed further in the following DAC circuit embodiments that utilizethe factorized DAC method.

Section 8—Description of FIG. 8

FIG. 8 is a simplified circuit schematic diagram illustrating anembodiment of an iDAC that utilizes the factorized iDAC method describedand illustrated in section 7 FIG. 7.

In FIG. 8, the illustrated factorized iDAC is comprising of threesubordinated factorized iDAC blocks DACt₈, DACm₈, and DACb₈ which areanalogous to DACt₇, DACm₇, and DACb₇ of FIG. 7. Moreover, in FIG. 8, thethree factor blocks Ft₈, Fm₈, and Fb₈ are analogous to Ft₇, Fm₇, and Fb₇of FIG. 7. As noted earlier, the embodiment of the factorized DAC methodis illustrated with combining three subordinated factorized iDACs (andtheir respective factor blocks) in FIG. 8. However, the factorizedmethod is flexible in utilizing, for example, two or four subordinatedfactorized iDACs (and their respective factor blocks), depending on theend-application's feature-benefit-cost requirements.

In FIG. 8, the factorized iDAC's reference current source I1 ₈ sets thegate-to-source voltage of M7 ₈ which is scaled and mirrored onto M1 ₈-M2₈, M3 ₈-M4 ₈, and M5 ₈-M6 ₈ which are a binary weighted current sourcenetworks, belonging to the three subordinated factorized iDACs: DACt₈,DACm₈, and DACb₈, respectively. The digital word Di₇ in FIG. 7 isanalogous FIG. 8's Di₈ digital word comprising of digital bits D6 ₈-D5₈-D4 ₈-D3 ₈-D2 ₈-D1 ₈. The digital words Dt₇, Dm₇, and Db₇ in FIG. 7 areanalogous to digital words D6 ₈-D5 ₈, D4 ₈-D3 ₈, and D2 ₈-D1 ₈ of FIG.8, respectively. Note that for clarity of illustration the factorizediDAC's resolution is arranged with 6-bit, but the resolution can behigher such as 16-bits. In FIG. 7, signals At₇, Am₇, and Ab₇ areanalogous to current signals designated as At₈, Am₈, and Ab₈ in FIG. 8,which are the current output signals of subordinated factorized iDACblocks DACt₈, DACm₈, and DACb₈, respectively. In FIG. 7, designatedsignals Ft₇×At₇, Fm₇×Am₇, and Fb₇×Ab₇ are analogous to current signalsdesignated as Ft₈×At₈, Fm₈×Am₈, and Fb₈×Ab₈ in FIG. 8, which are thecurrent output signals of factor blocks Ft₈, Fm₈, and Fb₈, respectively.In FIG. 8, current output signals of factor blocks Ft₈, Fm₈, and Fb₈ arecoupled (summed) at node A₈. As such the factorized iDAC output currentsignal is A₈=Ft₈×At₈ Fm₈×Am₈+Fb₈×Ab₈.

Given that the three subordinated factorized iDACs (i.e., DACt₈, DACm₈,and DACb₈) in FIG. 8 are identical, only the subordinated factorizedDACt₈'s operation is briefly described. Let the I1 ₈=w as the DACt₈'sreference analog current input signal, which is scaled and mirrored ontothe subordinated factorized DACt₈'s current source network comprising ofI_(N1) ₈ =2w and I_(N2) ₈ =1w. Consider that M1 ₈ and M2 ₈ are cascadedby M8 ₈ and M9 ₈ (biased with V1 ₈), respectively, to raise the currentsources output impedance. The I_(N1) ₈ =I_(N8) ₈ =2w is coupled with acurrent switch comprising of M15 ₈ and M21 ₈. The M15 ₈ is biased at afixed voltage V2 ₈+V1 ₈ that can be biased at approximately(V_(DD)+V_(SS))/2, which would enable M15 ₈, M21 ₈ to switch I_(N8) ₈=I_(N1) ₈ to two paths: When D6 ₈ is in the low (V_(SS)) states, I_(N1)₈ flows through M15 ₈ (that is turned on) and onto M27 ₈. The aim ofdiode connected M27 ₈ is to substantially equalize the drain terminalvoltage of M8 ₈ at roughly V_(DD)−V_(GSpmos), while D6 ₈ is toggledbetween high or low states, which improves the iDAC's dynamic response.Similarly, I_(N2) ₈ =I_(N9) ₈ =1w is coupled with a current switchcomprising of M16 ₈ and M22 ₈. Also, M16 ₈ is biased at a fixed voltageV2 ₈+V1 ₈. When D5 ₈ is in the high states, the I_(N2) ₈ flows throughM22 ₈ and again onto node At₈. When D5 ₈ is in the low states, theI_(N2) ₈ flows through M16 ₈ and onto the diode connected M27 ₈, whichagain substantially equalizes the drain terminal voltage of M8 ₈ atroughly V_(DD)−V_(GSpmos), when D5 ₈ is toggled between high or lowstates, which improves the iDAC's dynamic response. Notice that thefull-scale current signal flowing through the node designated as A_(t8)is 2×I1 ₈+1×I1 ₈=3×I1 ₈=3w, which is the full-scale output currentsignal for subordinated factorized DACt₈.

Similarly, the current signals through nodes designated as Am₈ and Ab₈(which are generated by the subordinated factorized DACm₈ and DACb₈,respectively) both have a full-scale current of 3w. Consider that tr₈,mr₈, and br₈ are the equivalent full-scale reference signal for thesubordinated factorized DACt₈, DACm₈ and DACb₈, respectively, which areanalogous to the terminology tr₇, mr₇, br₇ described in section 7, FIG.7. Since the three subordinated factorized iDAC's reference analogsignals (full-scale values) are arranged substantially equally (i.e.,equivalent tr₈=mr₈=br₈=3w), then the three other factor scales areprogrammed according to: Fm₈=1 as base value, Ft₈=2^(t) ⁸/(tr₈/mr₈)=2²/(1)=4 and Fb₈=(½^(m) ⁸ )×(mr₈/br₈)=(½²)×(1)=¼, taking intoconsideration that DACt₈ is a 2-bit DAC (t₈=2) and DACm₈ is a 2-bit DAC(m₈=2).

Accordingly, the full-scale value of the factorized iDAC which isA₈=Ft₈×At₈+Fm₈×Am₈+Fb₈×Ab₈=4×3w+1×3w+¼×3w=w×15¾. Given that I1 ₈=w, thefull-scale value of A₈ can be adjusted in accordance with w×15¾ (fromnano amperes to milliamperes scales) depending on the applicationsrequirements.

As noted earlier, the accuracy of the factorized DAC is dominated bymatching of components in the signal path of the most significant bits(MSB). As such, design and FET layout care can help the matching betweenM1 ₈-M2 ₈ in the subordinated factorized DACt₈ block and matchingbetween M34 ₈-M35 ₈ in the Ft₈ block which arrange the factorized iDAC'sMSB and dominate the accuracy of the overall factorized DAC. Moreover,subordinated factorized DACt₈ can be arranged in a segmented fashion(disclosed next in section 9, FIG. 9) to improve accuracy and reduce theglitch.

Also, it would obvious to one skilled in the art to further reduce thesize and cost of FIG. 8's circuit by eliminating the cascoded FETs M28 ₈to M33 ₈ as well as M8 ₈ to M14 ₈ in applications where low powersupplies with low V_(DD) variations are available, and or low costcalibration (trimming) is available to adjust gain error and full-scale.

The benefits of factorized DAC, including that of factorized iDAC aresummarized below:

First, factorized iDAC is smaller than standard iDACs, and here is how:A standard binary weighted iDAC's current source network (as part of theiDAC's input-to-output transfer function network) is comprising ofscaled current sources as follows: the MSB current source sized at2⁵x=32x scaled through (2⁴x=16x, 2³x=8x, 2²x=4x, 2¹x=2×) to the LSBcurrent source cell sized at 2° x=lx, where x is an equivalent currentsource cell that carries an LSB current weight. As such, for a standard6-bit iDAC, about 63x current sources are required.

In comparison (setting aside the cascoded FETs and current switches), afactorized iDAC illustrated in FIG. 8 would require: 2x+1x, 2x+1x, 2x+1xcurrent source cells for the three subordinated factorized iDACs (DACt₈,DACm₈, and DACb₈) plus 4x+1x, 1x+1x, 1x+4x (equivalent size x currentsource cell) for the three current mirrors in factor blocks (Ft₈, Fm₈,and Fb₈). As such, for a 6-bit iDAC utilizing the factorized DAC method,21x equivalent current source cells are required, which is about 3 timessmaller than a conventional iDAC.

For higher resolution DACs, the factorized DAC method is even more areaefficient.

Second, dynamic response is faster than conventional iDACs becausefactorized DACs smaller sized input-to-output transfer function networkutilizes smaller FETs with smaller capacitances, which can be chargedand discharged faster.

Third, glitch is lower during code transitions compared to standardDACs, again because factorized DACs smaller input-to-output transferfunction network utilizes smaller devices that carry smallercapacitances, which inject fewer analog glitches to the output of theDAC during digital input code transitions.

Fourth, dynamic power consumption is lower because a factorized DAC'ssmaller sized FETs (in the input-to-output transfer function network)would consume less dynamic current to drive smaller devices duringdigital input code transitions.

Fifth, utilizing the factorized DAC method in a current-mode DAC (iDAC)is inherently fast.

Sixth, factorized iDAC can operate with low power supply since itsoperating headroom can be limited by a FET's VGS+VDS.

Seventh, utilizing the factorized iDACs in subthreshold region canfurther reduce power consumption and lower power supply voltage.

Eight, factorized iDAC can be programmed for a non-linear (e.g.,logarithmic or square) input-to-output transfer function.

Ninth, running the CMOSFETs in subthreshold enables the factorized iDACto operate with ultra-low currents, low power supply, and ultra-lowpower consumption suitable for mobile applications, especially in AI andML applications that require numerous ultra-low power and low powersupply DACs for computation.

Tenth, neither any capacitors nor any resistors are needed, whichfacilitates fabricating the factorized iDAC in standard digital CMOSmanufacturing factory that is low cost, main-stream and readilyavailable for high-volume mass production applications, and proven forbeing rugged and having high quality.

Eleventh, factorized iDAC can be arranged free of clock, suitable forasynchronous (clock free) computation.

Twelfth, factorized iDAC can utilize same type of MOSFET current sourcesand MOSFET switches that are symmetric, matched, and scaled. This traitfacilitates devices parameters to track each other over process,temperature, and operating condition variations. Accordingly, the iDAC'stemperature coefficient, power supply coefficient, and AC power supplyrejection performance can be enhanced.

Thirteenth, the embodiment disclosed here is not restricted by FETshaving to operate either in saturation (high-currents) or subthreshold(low currents). For example, some analog signal processing units rely onoperating transistors in the subthreshold regions which restricts thedynamic range of analog signal processing circuits to low currentsignals. Also, some other analog signal processing units rely onoperating transistors with high currents in the saturation regions whichrestricts the dynamic range of analog signal processing circuits tohigher current signals.

Section 9—Description of FIG. 9

FIG. 9 is a simplified circuit schematic diagram illustrating anotherembodiment of an iDAC that combines the factorized and floating iDACmethods described in sections 7 and 1, and illustrated FIGS. 7 and 1,respectively.

The three subordinated iDACs in FIG. 9 utilize a combination of both thefactorized DAC method and the floating iDAC methods. Also, the topsubordinate DACt₉ utilizes floating iDAC method as well as segmentationto improve accuracy and reduce glitch associated with digital input codetransitions.

In FIG. 9 illustration, the factorized floating iDAC is comprising ofthree factorized floating subordinated iDACs depicted in blocks DACt₉,DACm₉, and DACb₉ (which are analogous to DACt₈, DACm₈, and DACb₈ of FIG.8). The factor blocks Ft₉, Fm₉, and Fb₉ are analogous to Ft₈, Fm₈, andFb₈ of FIG. 8. Notice that the digital input word Di₈ comprising of thedigital bits D6 ₈ to D1 ₈ in FIG. 8 are analogous to the factorizedfloating iDAC's digital input word Di₉ comprising of the digital bits D6₉ to D1 ₉ of FIG. 9, respectively. Again, bear in mind that for clarityof illustration the main factorized floating iDAC in FIG. 9 is arrangedwith 6-bit of resolution (comprising of the three 2-bit factorizedfloating subordinated iDACs: DACt₉, DACm₉, and DACb₉) but the factorizedfloating iDAC resolution can be higher, such as 16-bit. Also, it wouldbe obvious to one skilled in the art that iDACs can be arranged withless than three factorized floating subordinated iDACs (e.g., two) ormore than three (e.g., four or five).

The factorized floating iDAC's reference current source I1 ₉ sets thegate-to-source voltage of M4 ₉ which is scaled and mirrored onto M1 ₉,M2 ₉, and M3 ₉ which program the full-scale weights of the threefactorized floating subordinated iDACs: DACt₉, DACm₉, and DACb₉,respectively. Also notice that signals At₈, Am₈, and Ab₈ in FIG. 8 areanalogous to current signals designated as At₉, Am₉, and Ab₉ in FIG. 9which are the current output signals of the three subordinated iDACblocks DACt₉, DACm₉, and DACb₉, respectively. In FIG. 8, designatedsignals Ft₈×At₈, Fm₈×Am₈, and Fb₈×Ab₈ analogous to current signalsdesignated as Ft₉×At₉, Fm₉×Am₉, and Fb₉×Ab₉ in FIG. 9, which are thecurrent output signals of factor blocks Ft₉, Fm₉, and Fb₉, respectively.In FIG. 9, current output signals of factor blocks designated as Ft₉,Fm₉, and Fb₉ are coupled (summed) at node A₉. As such the factorizedfloating iDAC output current signal is A₉=Ft₉×At₉+Fm₉×Am₉+Fb₉×Ab₉.

As noted earlier, the three factorized floating subordinated iDACs inFIG. 9 utilize a combination of both the factorized DAC method(described in section 7, FIG. 7), and the floating iDAC method(described in section 1, FIG. 1). In FIG. 9, a central reference currentI1 ₉=w flows through M4 ₉ that is sized at 1x, which programs I_(M49)=wthat is mirrored and scaled onto: M1 ₉ sized at 4x with I_(M1) ₉ =4×w,M2 ₉ sized at 2x with I_(M1) ₉ =2×w, and M3 ₉ sized at 1x with I_(M1) ₉=1×w. Consider that I_(M1) ₉ , I_(M2) ₉ , and I_(M3) ₉ are the referenceanalog signals tr₉=4w, mr₉=2w, and br₉=1w (analogous to the terminologytr₇, mr₇, br₇ described in section 7, FIG. 7) that are applied to thefactorized floating subordinated DACt₉, DACm₉ and DACb₉, respectively,which also set the said three factorized floating subordinated iDAC'sfull-scale current output signals through nodes designated as At₉, Am₉and Ab₉, respectively. As such, the three factor scales are programmedaccording to: For Fm₉=1 as base factor scale, Ft₉=2^(t) ⁹/(tr₉/mr₉)=2²/(2)=2 and Fb₉=(½^(m) ⁹ )×(mr₉/br₉)=(½²)×(2)=½, alsoconsidering that DACt₉ is a 2-bit iDAC (t₉=2) and DACm₉ is a 2-bit iDAC(m₉=2).

Accordingly, the full-scale value of the factorized floating iDAC outputis A₉=Ft₉×At₉+Fm₉×Am₉+Fb₉×Ab₉=2×4w+1×2w+½×1w=w×10½. Given that I1 ₉=w,the full-scale value of A₉ output signal can be adjusted (from nanoamperes to milliamperes scales) depending on the applicationsrequirements.

Notice that V1 ₉ biases the floating current sources M5 ₉ to M11 ₉. Forapplications where high-accuracy and higher iDAC output currents may berequired, instead of one voltage source such as V1 ₉, up to threevoltage sources can be utilized: such as one for each group of floatingcurrent sources M5 ₉ to M7 ₉, one for M4 ₉ to M5 ₉, and one for M10 ₉ toM12 ₉. In doing so, the V_(DS) or drain-to-source voltages of M1 ₉ to M4₉ would match which reduces scaled second order systematic error dueV_(is) mismatch between M1 ₉ to M4 ₉ currents. The current switches S1 ₉to S7 ₉ (when in their off states) are terminated onto a diode connectedM13 ₉ which is a VGS_(PMOS) below V_(DD) that roughly matches (to firstorder) the VGS_(PMOS) of diode connected M20 ₉, M22 ₉, and M24 ₉. Assuch, the transient and dynamic performance of the iDAC is improvedsince the drain terminal of FETs M5 ₉ to M11 ₉ are roughly balanced atV_(DD)−VGS_(PMOS) as the iDAC's codes toggle between on and off states.

Additionally, DACt₉ is arranged with segmentation to improve accuracysince DACt₉ carries the analog weight of the first 2 most significantbits. Here, D6 ₉ and D5 ₉ are fed to a 2-to-3 bit encoder (comprising ofAND1 ₉ and OR1 ₉) whose digital outputs control the DACt₉'s currentswitches. As such, the DACt₉'s substantially equal current sourcesegments (I_(M5) ₉ , I_(M6) ₉ , and I_(M7) ₉ ) are turned on-or-off oneat a time (e.g., thermometer fashion), which improves accuracy andlowers the digital input code to analog output glitching. As notedearlier, the motivation for segmenting the MSB (as noted earlier) isthat the accuracy of the factorized DAC is dominated by the MSBinput-to-output transfer function network.

Excluding the cascoded current mirrors and current switches, thedisclosed 6-bit iDAC in FIG. 9 occupies the equivalent area of about 24xcurrent source cells, compared to that of a standard iDAC requiringabout 63x current source cells, where x is an equivalent current sourcecell that carries an LSB current weight. In summary, some of thebenefits of the factorized floating iDAC embodiment illustrated in FIG.9 includes some of the benefits of the floating iDAC described insection 2, FIG. 2, in addition to some of the benefits of the factorizediDAC described in section 8, FIG. 8. Moreover, arranging the MSBfactorized iDAC (DACt₉) in a segmented manner has the benefit ofimproved accuracy as well as lowering the iDAC's glitch.

Section 10—Description of FIG. 10

FIG. 10 is a simplified circuit schematic diagram illustrating anotherembodiment of another iDAC that utilizes the factorized and floating DACmethods described in sections 7 and 1, and illustrated FIGS. 7 and 1,respectively.

The two subordinated iDACs in FIG. 10 utilize a combination of both thefactorized DAC method and the floating iDAC methods. The DACt₁₀,utilizes conventional 2-bit iDAC that is segmented for improve accuracyand lower glitch associated with the first 2 MSBs code transitions.

In FIG. 10, the illustrated factorized floating iDAC is comprising oftwo subordinated iDACs illustrated in blocks DACt₁₀ (subordinatedsegmented factorized iDAC) and DACb₁₀ (subordinated factorized floatingiDAC) that operate in conjunction with the factor blocks Ft₁₀, and Fb₁₀.The iDAC's digital input word D_(i10) comprising of the digital bits D1₁₀ to D6 ₁₀, respectively. Again, bear in mind that for clarity ofillustration the overall factorized floating iDAC in FIG. 10 is arrangedwith 6-bit of resolution (comprising of DACt₁₀ that is a subordinated2-bit segmented factorized iDACs, and the factorized floating 4-bitDACb₁₀) but overall resolution of the factorized floating iDAC can behigher, such as 16-bit.

In FIG. 10, signals At₁₀ and Ab₁₀ depict the current output signals ofthe two subordinated iDAC blocks DACt₁₀ and DACb₁₀, respectively.Current signals designated as At₁₀×Ft₁₀ and Ab₁₀×Fb₁₀ are the currentoutput signals of factor blocks Ft₁₀ and Fb₁₀, respectively. In FIG. 10,current output signals of factor block Ft₁₀ and Fb₁₀ are coupled(summed) at node A₁₀. As such, in FIG. 10, the factorized floating iDACoutput current signal is A₁₀=Ft₁₀×At₁₀+Fb₁₀×Ab₁₀.

The iDAC's reference current source in FIG. 10 is I1 ₁₀ which programsthe gate-to-source voltage of M6 ₁₀ that is scaled and mirrored onto M1₁₀, M2 ₁₀, and M3 ₁₀, which together program the full-scale weights ofDACt₁₀. Moreover, the gate-to-source voltage of M6 ₁₀ is mirrored ontoM4 ₁₀, and M5 ₁₀, which together program the full-scale weight ofDACb₁₀. Note that the drain current of M5 ₁₀ that is I_(M5) ₁₀ ,supplies the floating current to the floating section of the DACb₁₀comprising of M11 ₁₀, M12 ₁₀, M13 ₁₀, and M14 ₁₀, which are binaryscaled at 4x, 2x, 1x, and 1x, respectively. Let's set I1 ₁₀=w, thenI_(M4) ₁₀ =I_(M5) ₁₀ =I_(M6) ₁₀ =I1 ₁₀=I_(M10) ₁₀ =w, I_(M11) ₁₀ =w/2,I_(M12) ₁₀ /4=w/4, I_(M13) ₁₀ =w/8, and I_(M14) ₁₀ =w/8. Also, M1 ₁₀, M2₁₀, and M3 ₁₀ sized at 1x with I_(M1) ₁₀ =I_(M2) ₁₀ =I_(M3) ₁₀ =I_(M6) ₉=1×w. Accordingly, the full scale value of At₁₀ which is the outputcurrent for DACt₁₀ is then 3w that also represents tr₁₀. The full scalevalue of Ab₁₀ which is the output current for DACb₁₀ is 2w that alsorepresents br₁₀. Since there are only a top iDAC (DACt₁₀) and a bottomiDAC(DACb₁₀), the programming of factor values are more straightforward: The LSB weight of DACt₁₀ is w and the LSB weight of DACb₁₀ isw/8, which makes their ratio=8. Considering that DACt₁₀ is a 2-bit iDAC(t₁₀=2), then 2^(t) ¹⁰ =4, which computes to 4/8=½ or Ft₁₀=1 and Fb₁₀=½for current mirrors with the smallest FET ratio. Accordingly, thefull-scale value of the factorized iDAC outputA₁₀=Ft₁₀×At₁₀+Fb₁₀×Ab₁₀=1×3w+½×2w=w×4. Given that I1 ₁₀=w, thefull-scale value of A₁₀ output signal can be adjusted (from nano-amperesto milli-amperes scales) depending on the applications requirements.

Notice that V1 ₁₀ and V2 ₁₀ bias the floating current sources M7 ₁₀ toM9 ₁₀ of DACt₁₀, and M10 ₁₀ to M14 ₁₀ of DACb₁₀, respectively. By havingseparate V1 ₁₀ and V2 ₁₀, the V_(DS) or drain-to-source voltages of M7₁₀ to M14 ₁₀ would match better which reduces (scaled) second ordersystematic error (due to drain-to-source or FET's V_(DS) mismatch)between M1 ₁₀ to M5 ₁₀ currents. Also, as stated in the prior section,the iDAC's current switches (iSWs) S1 ₁₀ to S7 ₁₀, in their off states,are terminated onto a diode connected M15 ₁₀ which is a VGS_(PMOS)(below V_(DD)) that roughly matches the VGS_(PMOS) of diode connectedM20 ₁₀ and M22 ₁₀. As such, the transient and dynamic performance of thefactorized floating iDAC is improved since the drain terminal of FETs M7₁₀ to M13 ₁₀ are roughly balanced at V_(DD)−VGS_(PMOS) as the iDAC'scodes toggle between on and off states.

Additionally, DACt₁₀ is arranged with segmentation to improve accuracy.The two upper MSBs, D6 ₁₀ and D5 ₁₀ are fed to a 2-to-3 bit encoder(comprising of AND1 ₁₀ and OR1 ₁₀) whose digital output control theDACt₁₀'s switches. As such, the DACt₁₀'s substantially equal currentsource segments (I_(M1) ₁₀ , I_(M2) ₁₀ , and I_(M3) ₁₀ ) turn on-or-offone at a time (e.g., in a thermometer fashion), which improves accuracyand lowers digital input code to analog output glitching. As statedearlier, the motivation for segmenting the MSB (as noted earlier) isthat the accuracy of the factorized DAC is dominated by the accuracy ofthe MSB signal path.

Excluding the cascoded current mirrors and current switches, thedisclosed 6-bit iDAC in FIG. 10 occupies the equivalent area of about18x current source cells, compared to that of a conventional iDACrequiring about 63x current source cells, where x is an equivalentcurrent source cell that carries an LSB current weight. In summary, someof the benefits of the factorized floating iDAC embodiment illustratedin FIG. 10 includes some of the benefits of the floating iDAC describedin section 2, FIG. 2, in addition to some of the benefits of thefactorized iDAC described in section 8, FIG. 8. Moreover, arranging theMSB factorized iDAC (DACt₁₀) in a segmented manner has the benefit ofimproved accuracy as well as lowering the iDAC's glitch.

Section 11—Description of FIG. 11

FIG. 11 is a simplified circuit schematic diagram illustrating anembodiment of a mixed-signal current-mode digital-input to analog-outputmultiplier (XD_(i)I_(o)) comprising of a first iDAC whose outputsupplies the reference input to a second iDACs, wherein the first andsecond iDACs utilize the factorized and floating DAC methods illustratedFIG. 7, and FIG. 1, respectively.

As noted earlier, a simplified transfer function for an

${{{iDAC}\mspace{14mu}{is}\text{:}\mspace{14mu} I_{o}} = {{l_{R}{\sum\limits_{i = 1}^{k}{D_{i}/2^{i}}}} = {{\left( {I_{R}/2^{k}} \right){\sum\limits_{i = 1}^{k}{D_{i} \times 2^{i - 1}}}} = {\Delta_{R}{\sum\limits_{i = 1}^{k}{D_{i} \times 2^{i - 1}}}}}}},$where for the iDAC, I_(o) is the analog output current, I_(R) is thereference input current that can set the full-scale value of I_(o),D_(i) is the digital input word (that is k-bits wide), andΔ_(R)=(I_(R)/2^(k)) represents an analog LSB current weight for I_(o).For example, for a 6-bit iDAC, k=6, and full scale value of I_(o) set tosubstantially equal I_(R)=64 nA, then LSB of the iDAC which isΔ_(R)=(I_(R)/2^(k))=Δ_(R)=(64 nA/2⁶)=1 nA.

A simplified transfer function of a multiplier XD_(i)I_(o) where aY-iDAC's output supplies the reference input to a second X-iDAC is asfollows:

$I_{oy} = {{I_{Ry}{\sum\limits_{y = 1}^{m}{D_{y}/2^{y}}}} = {{\left( {I_{Ry}/2^{m}} \right) \times {\sum\limits_{y = 1}^{m}{D_{y} \times 2^{y - 1}}}} = {\Delta_{Ry} \times {\sum\limits_{y = 1}^{m}{D_{y} \times 2^{y - 1}}}}}}$where the analog output current is I_(oy), the reference input currentis I_(RY) which can set the full-scale value of I_(oy), the digitalinput word (that is m-bits) wide is D_(y), and Δ_(Ry)=(I_(Ry)/2^(m))represents an analog LSB current weight of I_(oy).

Similarly, for the X-iDAC

$I_{ox} = {{I_{Rx}{\sum\limits_{x = 1}^{n}{D_{x}/2^{x}}}} = {{\left( {I_{Rx}/2^{n}} \right) \times {\sum\limits_{x = 1}^{n}{D_{x} \times 2^{x - 1}}}} = {\Delta_{\;{Rx}} \times {\sum\limits_{x = 1}^{n}{D_{x} \times 2^{x - 1}}}}}}$where the analog output current is I_(ox), the reference input currentis I_(Rx) which can set the full-scale value of I_(ox), the digitalinput word (that is n-bits) wide is D_(x), and L_(Rx)=(I_(Rx)/2^(n)) isan analog LSB current weight of I_(ox).

By feeding the output current of Y-iDAC onto the reference input of theX-iDAC, where

${I_{Rx} = {I_{oy} = {I_{Ry}{\sum\limits_{y = 1}^{m}{D_{y}/2^{y}}}}}},$the following transfer function is realized:

$I_{ox} = {\left( {l_{Ry}{\sum\limits_{y = 1}^{m}{D_{y}/2^{y}}}} \right) \times {\left( {\sum\limits_{x = 1}^{n}{D_{x}/2^{x}}} \right).}}$As such a digital-input to analog-current-output multiplier XD_(i)I_(o)is realized where

${\left( {\sum\limits_{y = 1}^{m}{D_{y}/2^{y}}} \right) \times \left( {\sum\limits_{x = 1}^{n}{D_{x}/2^{x}}} \right)} = {I_{ox}/{I_{Ry}.}}$

On the right hand-side of FIG. 11, the Y digital-input Dy₁₁ (that ism-bits wide where m=6 for illustrative clarity) is applied to a Y-iDAC,whose analog current output is Ay₁₁=I_(oY). The Y-iDAC utilizes acombination of floating and factorizing DAC methods, and it is comprisedof top, middle, and bottom iDACs and Factor blocks: DAC_(ty) ₁₁ & F_(ty)₁₁ , DAC_(my) ₁₁ , F_(my) ₁₁ , and DAC_(by) ₁₁ & F_(by) ₁₁ . In FIG. 11,for example, the upper half of DAC_(my) ₁₁ & F_(my) ₁₁ block iscomprising of the Factor function F_(my) ₁₁ , and the lower half ofDAC_(ty) ₁₁ & F_(ty) ₁₁ block is comprising of the subordinated iDACfunction DAC_(my) ₁₁ , and so on. For Y-iDAC, a reference current I1 ₁₁is mirrored by M8 ₁₁ onto M7 ₁₁ which supplies the reference current(via the floating DAC method) onto the three 2-bit subordinatedfactorized floating iDACs: DAC_(ty) ₁₁ (comprising of M15 ₁₁-M16 ₁₁),DAC_(my) ₁₁ (comprising of M17 ₁₁-M18 ₁₁), and DAC_(by) ₁₁ (comprisingof M19 ₁₁-M20 ₁₁). The digital word Dy₁₁ (that is m=6 bits wide) isapplied to the respective Y-iDAC current switches S7 ₁₁ through S12 ₁₁.The Y-iDAC utilizes NMOSFETs for its three 2-bit subordinated factorizedfloating iDACs sub-blocks (DAC_(ty) ₁₁ , DAC_(my) ₁₁ , and DAC_(by) ₁₁ )whose output are fed onto diode-connected PMOSFETs M33 ₁₁, M35 ₁₁, andM37 ₁₁, respectively, which are the inputs of its three Factorsub-blocks (F_(ty) ₁₁ , F_(my) ₁₁ , and F_(by) ₁₁ ), respectively.Similar to the FIG. 8 in section 8, for illustrative clarity m=6 in FIG.11 (but m can be as high as 16-bits), and also similarly the factorvalues for F_(ty) ₁₁ , F_(my) ₁₁ , and F_(by) ₁₁ (current mirrors) are4x, 1x, and ¼x, respectively.

Also, note for example, when bit D1 y ₁₁ (the MSB of Y-iDAC, in thiscase) is off, then the off S7 ₁₁ couples the drain-terminal of M15 ₁₁(i.e., I_(M15) ₁₁ ) to a bias-voltage (V_(GS) _(P) that is a PMOSgate-to-source voltage below V_(DD), which is not shown for illustrativeclarity). The bias-voltage V_(GS) _(P) biases the current switches S7 ₁₁through S12 ₁₁, in a similar arrangement (and in this respect, similarto the iDAC's switch arrangement illustrated in FIGS. 8, 9, and 10) whenthe current switches are in off states.

Consider that diode connected NMOS M₂₁₁₁ are scaled and biased via I2 ₁₁(to generate a Vg_(M21) ₁₁ ) such that M1 ₁₁ to M7 ₁₁ have enoughdrain-to-source voltage head-room to remain in saturation, consideringgate-to-source voltage drop of M9 ₁₁ through M20 ₁₁. Similarly, diodeconnected PMOS M32 ₁₁ are scaled and biased via I2 ₁₁ (to generate aVg_(M32) ₁₁ ) such that M33 ₁₁ to M38 ₁₁ have enough drain-to-sourcevoltage head-room to remain is saturation, considering gate-to-sourcevoltage drop of M23 ₁₁ through M31 ₁₁.

The output of the Y-iDAC that is Ay₁₁=I_(oy) supplies the referencecurrent (via the floating DAC method) onto X-iDAC which is describednext.

On the left hand-side of FIG. 11, the X digital-input Dx₁₁ (that isn-bits wide where n=6 for illustrative clarity) is applied to a X-iDAC,whose analog current output is Ay₁₁×Ax₁₁=I_(ox). The X-iDAC is thecomplementary version of Y-iDAC described earlier, and it utilizes acombination of floating and factorizing DAC methods, and it is comprisedof top, middle, and bottom iDACs and Factor blocks: DAC_(tx) ₁₁ & F_(tx)₁₁ , DAC_(mx) ₁₁ & F_(mx) ₁₁ , and DAC_(bx) ₁₁ & F_(x). In FIG. 11, forexample, the upper half of DAC_(mx) ₁₁ & F_(mx) ₁₁ block is comprisingof the Factor function F_(mx) ₁₁ , and the lower-half of DAC_(tx) ₁₁ &F_(tx) ₁₁ is comprising of the subordinated DAC_(mx) ₁₁ , and so on. Theoutput of Y-iDAC or Ay₁₁=I_(oy) supplies the reference current ontoX-iDAC's three of 2-bit factorized floating subordinate iDACs: DAC_(tx)₁₁ (comprising of M23 ₁₁-M24 ₁₁), DAC_(mx) ₁₁ (comprising of M25 ₁₁-M26₁₁), and DAC_(bx) ₁₁ (comprising of M27 ₁₁-M28 ₁₁). The digital wordDx₁₁ (that is also m=n=6 bits wide) is applied to the respective X-iDACcurrent switches S1 ₁₁ through S6 ₁₁. The X-iDAC utilizes PMOSFETs forits three 2-bit DAC_(tx) ₁₁ , DAC_(mx) ₁₁ , and DAC_(bx) ₁₁ whose outputare fed onto diode-connected NMOSFETs M1 ₁₁, M3 ₁₁, and M5 ₁₁,respectively, which are the inputs of its three Factor blocks F_(tx) ₁₁, F_(mx) ₁₁ , and F_(bx) ₁₁ , respectively. Similar to the FIG. 8 insection 8, for illustrative clarity n=6 in FIG. 11 (but n can be as highas 16-bits), and also similarly the factor scales or values for F_(tx)₁₁ , F_(mx) ₁₁ , and F_(bx) ₁₁ (current mirrors) are 4x, 1x, and ¼x,respectively.

Also, note for example, when bit D1 x ₁₁ (the MSB of X-iDAC, in thiscase) is off, then the off S1 ₁₁ couples the drain-terminal of M23 ₁₁(i.e., I_(M23) ₁₁ ) to a bias-voltage (V_(GS) _(N) ) that is a NMOSgate-to-source voltage above V_(SS). The bias-voltage (V_(GS) _(N) ) isnot shown for clarity of illustration, but V_(GS) _(N) biases thecurrent switches S1 ₁₁ through S6 ₁₁, in a similar arrangement (and inthis respect, similar to the iDAC's switch arrangement illustrated inFIGS. 8,9, and 10) when the current switches are in off states.

Accordingly, a digital-input to analog-current-output multiplierXD_(i)I_(o) is realized where

${{\left( {\sum\limits_{y = 1}^{m}{D_{y}/2^{y}}} \right) \times \left( {\sum\limits_{x = 1}^{n}{D_{x}/2^{x}}} \right)} = {I_{ox}/I_{Ry}}},$where m=n=6, and Ay₁₁×Ax₁₁=I_(ox) which is the analog representation ofmultiplying two digital codes D_(y)=Dy₁₁ and D_(x)=Dx₁₁. Bear in mindthat I_(Ry) represents a reference weight for the multiplier XD_(i)I_(o)which is a scaled multiple (g) of I1 ₁₁. For example, if I1 ₁₁=i forY-iDAC, then the full scale output current for each of sub-iDAC blocksDAC_(ty) ₁₁ , DAC_(my) ₁₁ , and DAC_(by) ₁₁ would be

${\frac{i}{9}\left( {{1x} + {2x}} \right)} = {i/3}$which is factored by 4x, 1x, and x/4 by its respective blocks F_(ty) ₁₁, F_(my) ₁₁ , and F_(by) ₁₁ . Consider that x=1 is programmed as thebase factor scale in current mirrors of the subordinate iDAC and Factorblocks. Accordingly, Y-iDAC's full scale output value of A_(y11) is

${{\frac{i}{3} \times \left( {{4x} + {1x} + \frac{x}{4}} \right)} = {i \times}}{5.25/3.}$Similarly, for the X-iDAC, the full scale output current for each ofsubordinated iDAC blocks DAC_(tx) ₁₁ , DAC_(mx) ₁₁ , and DAC_(bx) ₁₁would be

${{\frac{A_{y11}}{9}\left( {{1x} + {2x}} \right)} = {A_{y11}/3}},$which is also factored by 4x, 1x, and x/4 by its respective factorblocks F_(tx) ₁₁ , F_(mx) ₁₁ , and F_(bx) ₁₁ . As noted earlier, theoutput of Y-iDAC, which is A_(y11) that is fed onto X-iDAC for itsreference current signal. Therefore, X-iDAC's full scale output value of

${{A_{y11} \times A_{x11}} = {{\frac{A_{y11}}{3} \times \left( {{4x} + {1x} + \frac{x}{4}} \right)} = {{A_{y11} \times \frac{{5.2}5}{3}} = {{i \times \frac{{5.2}5}{3} \times \frac{5.25}{3}} = {i \times \left( \frac{5.25}{3} \right)^{2}}}}}},\mspace{14mu}{{{where}\mspace{14mu} g} = {\left( \frac{{5.2}5}{3} \right)^{2}.}}$As such,

$I_{Ry} = {{i \times g} = {{I\; 1_{11} \times g} = {I\; 1_{11} \times \left( \frac{5.25}{3} \right)^{2}}}}$represents the reference weight for the multiplier XD_(i)I_(o).

In summary some of the benefits of the XD_(i)I_(o) utilizing thefactorizing iDAC method are as follows:

First, the XD_(i)I_(o) utilizing the factorizing iDAC (described insection 8 of FIG. 8) saves area and helps reduce FET sizes which savesdie are, lowers cost, and also lowers the capacitance that can becharged and discharged faster in the iDAC's current reference networkwhich in turn improve the transient response of the XD_(i)I_(o).

Second, the XD_(i)I_(o) operating in current-mode, which inherently runsfast.

Third, voltage swings in current-mode signal processing are small, whichenables operating the XD_(i)I_(o) with lower power supply voltage. Also,factorized iDAC utilized in XD_(i)I_(o) can operate with low powersupply since its operating headroom can be limited by a FET's VGS+VDS.

Fourth, operating at low supply voltage reduces power consumption of theXD_(i)I_(o). Moreover, Running the CMOSFETs in subthreshold enables thefactorized iDAC used in the in XD_(i)I_(o) to operate with ultra-lowcurrents, low power supply, and ultra-low power consumption suitable formobile applications, especially in AI and ML applications that requirenumerous XD_(i)I_(o) that are ultra-low power and operate on low powersupply for computation.

Fifth, by substantially equalizing the terminal voltages at the positiveand negative current output of the factorizing iDAC would improve thetransient response of the disclosed XD_(i)I_(o) and reduces glitch.

Sixth, the XD_(i)I_(o) needs neither any capacitors nor any resistors,which facilitates fabricating the XD_(i)I_(o) in standard digital CMOSmanufacturing factory that is low cost, main-stream and readilyavailable for high-volume mass production applications, and proven forbeing rugged and having high quality.

Seventh, the precision of the iDAC and hence that of the XD_(i)I_(o)multiplier can be improved by for example utilizing proper sized FETs inthe iDAC's current reference network or by utilizing current sourcesegmentation (along with digital binary-to-thermometer coding) in theiDAC's reference current transfer-function network.

Eighth, the XD_(i)I_(o) multiplier can lower resolution factorized iDACs(e.g., 3-bits or 5-bits) that occupy smaller areas, but have higheraccuracy (e.g., 8-bits of accuracy or 0.4%) which is beneficial forcost-performance. For example, higher than 3 of 5 bits of accuracy isattainable in standard CMOS fabrication. With proper W/L scaling of FETsused in the current source transfer-function of iDACs (8-bits ofaccuracy or), a ±0.4% matching that can be achievable. As such, thisdisclosure can utilize low resolution iDACs that occupy small areas andachieve higher accuracy multiplication at lower cost.

Ninth, glitch is lower during code transitions in XD_(i)I_(o) multiplierbecause factorized iDACs utilized in XD_(i)I_(o) are smaller given thatthe input-to-output transfer function network utilizes smaller devicesthat carry smaller capacitances, which inject fewer analog glitches tothe output of the XD_(i)I_(o) during digital input code transitions.

Tenth, dynamic power consumption is lower because the XD_(i)I_(o)multiplier utilizes factorized DAC that have smaller sized FETs (in theinput-to-output transfer function network) which would consume lessdynamic current to drive smaller FET devices during digital input codetransitions.

Eleventh, the XD_(i)I_(o) that utilizes factorized iDAC can be arrangedfree of clock, suitable for asynchronous (clock free) computation.

Twelfth, The XD_(i)I_(o) that utilizes same type of MOSFET currentsources and MOSFET switches in the respective factorized iDACs, whichare symmetric, matched, and scaled. This trait facilitates deviceparameters to track each other over process, temperature, and operatingconditions variations. Accordingly, the XD_(i)I_(o)'s temperaturecoefficient, power supply coefficient, and AC power supply rejectionperformance can be enhanced.

Thirteenth, the embodiment disclosed here is not restricted by FETshaving to operate either in saturation (high-currents) or subthreshold(low currents). For example, some analog signal processing units rely onoperating transistors in the subthreshold regions which restricts thedynamic range of analog signal processing circuits to low currentsignals. Also, some other analog signal processing units rely onoperating transistors with high currents in the saturation regions whichrestricts the dynamic range of analog signal processing circuits tohigher current signals

Section 12A & 12B—Description of FIG. 12A & FIG. 12B

FIG. 12, including FIG. 12A and FIG. 12B, is a (Simulation Program withIntegrated Circuits Emphasis) SPICE circuit simulation showing theinput-output and linearity waveforms of the mixed-signal current-modedigital-input to analog-current-output multiplier (XD_(i)I_(o)) that isillustrated in FIG. 11.

For the simulations of FIG. 12A and FIG. 12B, the digital signalsD_(y)=Dy₁₁=Y and D_(x)=Dx₁₁=X are spanned from full-scale to zero-scale(shown 1 as full-scale to 0 as zero-scale on the vertical axis) whenboth X, Y signals are ramped together in time from full-scale tozero-scale over 1 milli-second (shown on the horizontal axis). For thesimulations of FIG. 12B, for clarity of illustration, D_(y) and D_(y)are fed onto ideal iDACs and plotted as ‘D_(y) Analog Equivalent Signal’and ‘ D_(x) Analog Equivalent Signal’ that are displayed next toA_(y11)×A_(x11)=Y·X which is the resultant representation of analogoutput of the multiplier XD_(i)I_(o). FIG. 12A illustrates 10 runs ofmontecarlo (MC) simulation plotting the difference between an idealA_(y11)×A_(x11) and MC simulation of the transistor level circuit ofFIG. 11 that generates A_(y11)×A_(x11). FIG. 12B indicates the linearityof the multiplier XD_(i)I_(o).

The FETs in the iDAC and Factor blocks operate in the subthresholdregion where most of the mismatch between FETs is due to their thresholdvoltage (V_(TH0)) mismatch. In simulating of FIG. 11's circuit usingSPICE, wherein the simulations are depicted in FIG. 12A and FIG. 12B,the V_(TH0) statistical distribution for FETs is programmed as STAT CMOSV_(TH0) GAUSS 0.4%+3−3 cc=0.998, which indicated maximum I_(DS) mismatchof ˜±0.8% (for the 10 MC runs) between two arbitrary FETs (with the sameW/L as that of non-digital FETs in the iDAC and Factor blocks). The 10MC simulation runs in FIG. 12A, captured a maximum DNL of about ˜±0.3%(and a gain-error of about ˜±0.8% which is mostly due to the referencecurrent mirror mismatch). Note that for a 6-bit DAC, the resolution is½⁶=1.6%.

Section 13—Description of FIG. 13

FIG. 13 is a simplified circuit schematic diagram illustrating anembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is a mixed-signalcurrent-mode digital-input to analog-current-output (D_(i)I_(o)) scalarmultiply-accumulate (sMAC) circuit that utilizes current-modedigital-to-analog-converters (iDAC).

A simplified D_(i)I_(o) sMACiDAC's transfer function is

${\sum\limits_{m = 1}^{n}{s \times p_{m}}},$where a scalar (s) is multiplied with the sum of plurality (m=n) ofp_(m) weights. The disclosed embodiment of D_(i)I_(o) sMACiDAC utilizesthe distributive property, wherein multiplying the sum of two or more(plurality of) addends by a (scalar) number will give the same result asmultiplying each addend individually by the scalar) number and thenadding the products together. Accordingly, the disclosed embodiment ofD_(i)I_(o) sMACiDAC utilizes plurality of iDACs whose outputs coupledtogether in current-mode, which generates a summation current

$\left( {\sum\limits_{m = 1}^{n}p_{m}} \right)$that is then fed onto a current reference terminal of a scalar iDAC,whose output generate

$s \times {\sum\limits_{m = 1}^{n}p_{m}}$which can also be represented as

$\sum\limits_{m = 1}^{n}{s \times {p_{m}.}}$

To accomplish the above objective, the disclosed circuit of FIG. 13utilizes a plurality of digital input words (p_(D)) that are supplied toa plurality (m=n) of iDACs that generate a plurality of respectiveanalog output currents (p_(A)). The plurality of p_(A) analog outputcurrents are coupled together which generates a summation current signalthat is fed onto an input of a current controlled voltage source (CCVS).A voltage output of the CCVS is then fed onto a voltage controlledcurrent source (VCCS). Then a current output of the VCCS is fed onto a(current) reference terminal of a scalar iDAC whose digital input wordis S_(D). The scalar iDAC generates an analog (current) output signalwhich is the product of s_(A) (which represent the analog value ofS_(D)) multiplied by the sum of a plurality p_(Ai) (for m=n plurality)or

${s_{A} \times {\sum\limits_{m = 1}^{n}p_{Ai}}} = {\sum\limits_{m = 1}^{n}{s_{A} \times {p_{Ai}.}}}$

To further describe the disclosed D_(i)I_(o) sMACiDAC circuit embodimentof FIG. 13, let

${A_{w} = {A_{Rw} \times {\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}}}},{A_{x} = {A_{Rx} \times {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}}}},{{{and}\mspace{14mu} A_{y}} = {A_{Ry} \times {\sum\limits_{k = 1}^{y}{D_{k}/{2^{k}.}}}}}$For

A_(Rw) = A_(Rx) = A_(Ry) = A_(R), then${A_{w} + A_{x} + A_{y}} = {A_{R} \times {\left( {{\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}} + {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}} + {\sum\limits_{k = 1}^{y}{D_{k}/2^{k}}}} \right).}}$

The nomenclatures and terminologies used here are self-explanatory forone skilled in the art, but as an example for the w-channel iDAC, bearin mind that A_(w) is the analog output, A_(Rw) is the reference input,D_(i) is the digital input word that is w-bits wide, and so on.

If A_(R) is fed into reference input of scalar DACz₁₃, then

$A_{z} = {A_{R} \times {\sum\limits_{l = 1}^{z}{D_{l}/{2^{l}.}}}}$By feeding A_(w)+A_(x)+A_(y)=A_(Rz) into the reference input of scalarDACz₁₃, then it generates

$A_{o} = {{A_{Rz} \times {\sum\limits_{l = 1}^{z}{D_{l}/2^{l}}}} = {{\left( {A_{w} + A_{x} + A_{y}} \right) \times {\sum\limits_{i = 1}^{z}{D_{i}/2^{i}}}} = {\quad{\left\lbrack {A_{R} \times \left( {{\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}} + {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}} + {\sum\limits_{k = 1}^{y}{D_{k}/2^{k}}}} \right)} \right\rbrack \times {\sum\limits_{l = 1}^{z}{D_{l}/{2^{l}.}}}}}}}$

Therefore,

${{A_{o}/A_{R}} = {\left\lbrack \left( {{\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}} + {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}} + {\sum\limits_{k = 1}^{y}{D_{k}/2^{k}}}} \right) \right\rbrack \times {\sum\limits_{l = 1}^{z}{D_{l}/2^{l}}}}},$which can be represented in the analog domain asA_(o)/A_(R)=(A_(w)+A_(x)+A_(y))×A_(z). This represents multiplyingscalar z by the accumulation of w, x, and y.

In FIG. 13, the scalar iDACs and plurality of iDACs are shown with 3-bitof resolution i=j=k=l=3 and there are three (plurality) of iDACs, as anillustration and for clarity of description but not as a limitation ofthis disclosure. Resolution of iDACs can be up to 16-bits, and theplurality of iDACs can be a sea of iDACs and for example 1000 channels.

As noted earlier, an iDAC transfer function where A_(o)=I_(o) andA_(R)=I_(R) can be simplified to

$I_{o} = {{I_{R}{\sum\limits_{i = 1}^{n}{D_{i}/2^{i}}}} = {\left( {I_{R}/2^{n}} \right) \times {\sum\limits_{i = 1}^{n}{D_{i} \times {2^{i - 1}.}}}}}$For example, let's consider half-scale of a 3-bit wide digital wordcorresponding to the digital binary word D_(i)=100 or D₁=1, and D₂=D₃=0and letting I_(R) be 1 unit representing full-scale for I₀. In such anexample, the DAC's input-to-output transfer function would be asfollows: I₀=I_(R)×[D₁/2¹+D₂/2²+D₃×2³]=(I_(R))×[½¹+0/2²+0/2³]=I_(R)/2=½reference unit, which is ½ of full scale.

Here a more detailed description of embodiment of the D_(i)I_(o)sMACiDAC's circuit illustrated in FIG. 13 is provided. The referencecurrent I1 ₁₃=I_(r′) is applied to a diode connected M1 ₁₃ whoseVgs_(M1) ₁₃ biases the binary weighted current source network in each ofthree iDAC: DACw₁₃, DACx₁₃, and DACy₁₃. Notice that M12 ₁₃ and I2 ₁₃program the Vgs_(M12) ₁₃ that biases the cascoded FETs in binary currentsources of DACw₁₃, DACx₁₃, and DACy₁₃ to attain higher output impedanceof the respective iDAC's current network with higher accuracy, which canbe omitted to save area if lower V_(DD) with less variation is availablein the end-application.

A DACw₁₃ receives a digital word Dw₁₃, and generates an analog outputcurrent Aw_(n), wherein Vgs_(M1) ₁₃ biases M2 ₁₃, M3 ₁₃, and M4 ₁₃(according to their respective width-over-length or W/L scales a. x, 1x,2x, 4×) which programs the DACw₁₃'s binary weighted currents as a ratioof the I1 ₁₃=1_(r′). The DACw₁₃'s current switches S1 ₁₃, S2 ₁₃, and S3₁₃ steer the respective M2 ₁₃, M3 ₁₃, and M4 ₁₃ currents to either adiode connected M30 ₁₃ (which is coupled with the DACw₁₃'s I_(o) ⁻ port)or the DACw₁₃'s I_(o) ⁺ port (at Aw₁₃ signal) in accordance with thepolarity of digital word Dw₁₃ bits. As it would be clear to one skilledin the art, for example, when Dw₁₃'s MSB in on (high-state), then S1 ₁₃steers M2 ₁₃'s current (through the cascoded FET M14 ₁₃) onto theDACw₁₃'s I_(o) ⁺ port (carrying the analog output current Aw₁₃).Conversely, when Dw₁₃'s MSB in off (low-state), then S1 ₁₃ steers M2₁₃'s current (through the cascoded FET M14 ₁₃) onto the DACw₁₃'s I_(o) ⁻port and onto the diode connected M30 ₁₃ (through the cascoded FET M25₁₃).

A DACx₁₃ receives a digital word Dx₁₃, and generates an analog outputcurrent Ax₁₃, wherein Vgs_(M1) ₁₃ biases M5 ₁₃, M6 ₁₃, and M7 ₁₃(according to their respective width-over-length or W/L scales a. x, 1x,2x, 4×) which programs the DACx₁₃'s binary weighted currents as a ratioof the I1 ₁₃=I_(r′). The DACx₁₃'s current switches S4 ₁₃, S5 ₁₃, and S6₁₃ steer the respective M5 ₁₃, M6 ₁₃, and M7 ₁₃ currents to either thediode connected M30 ₁₃ (which is coupled with the DACx₁₃'s I_(o) ⁻ port)or the DACx₁₃'s I_(o) ⁺ port (for Ax₁₃ signal) in accordance with thepolarity of the Dx₁₃ bits.

A DACy₁₃ receives a digital word Dy₁₃, and generates an analog outputcurrent Ay₁₃, wherein Vgs_(M1) ₁₃ biases M8 ₁₃, M9 ₁₃, and M10 ₁₃(according to their respective width-over-length or W/L scales a. x, 1x,2x, 4×) which programs the DACy_(n)'s binary weighted currents as aratio of the I1 ₁₃=I_(r′). The DACy₁₃'s current switches S7 ₁₃, S8 ₁₃,and S9 ₁₃ steer the respective M8 ₁₃, M9 ₁₃, and M10 ₁₃ currents toeither the diode connected M30 ₁₃ (which is coupled with the DACy₁₃'sI_(o) ⁻ port) or the DACy_(n)'s I_(o) ⁺ port (for Ay₁₃ signal) inaccordance with the polarity of the Dy₁₃ bits.

As described earlier, the current outputs of DACw₁₃, DACx₁₃, and DACy₁₃are then summed to generate the output current summation Aw₁₃+Ax₁₃+Ay₁₃,which is fed onto the input of a CCVS (or current-to-voltage converteriTv₁₃) comprising of M26 ₁₃ and M31 ₁₃. An output of the CCVS isVgs_(M31) ₁₃ which is supplied to the input of a VCCS (orvoltage-to-current converter vTi₁₃) comprising of M32 ₁₃.

Consider that for a=1, the full scale output current for each of DACw₁₃,DACx₁₃, and DACy₁₃ is (4+2+1)×I_(r′)=7I_(r′).

Accordingly, the full-scale output current summation Aw₁₃+Ax₁₃+Ay₁₃would compute to 3×7I_(r′)=21I_(r′). The W/L's of M31 ₁₃ and M32 ₁₃(i.e., b.x and c.x) program the combined gain of iTv₁₃ and vTi₁₃ whichscales the sum of Aw₁₃+Ax₁₃+Ay₁₃ before the said sum is supplied to thereference input of a DACz₁₃. For clarity of description b=c=1 whichprovides a combined current scaling (net-gain) of 1 (through iTv₁₃ tovTi₁₃) for the sum of Aw₁₃+Ax₁₃+Ay₁₃ currents that are supplied to thereference input of a DACz₁₃.

The floating DACz₁₃ receives a digital word Dz₁₃, and generates ananalog output current at the DACz₁₃'s I_(o) ⁺ port that is the outputcurrent of D_(i)I_(o) sMACiDAC as being represented in the analog domainand proportional to A_(R″): A_(o)/A_(R″)=(A_(w)+A_(x)+A_(y))×A_(z). TheDACz₁₃'s current switches S10 ₁₃, S11 ₁₃, and S12 ₁₃ steer therespective M27 ₁₃, M28 ₁₃, and M29 ₁₃ currents to either a diodeconnected M11 ₁₃ (which is coupled with the DACz₁₃'s I_(o) ⁻ port) orthe DACz₁₃'s I_(o) ⁺ port in accordance with the polarity of the Dz₁₃bits.

As indicated earlier, for a=b=c=1, then A_(R″) is a scaled referencecurrent where A_(R″)=21I_(r′). Notice that DACz₁₃ utilizes a floatingiDAC method that is disclosed in FIG. 1 section 1. Also note that M24 ₁₃and I2 ₁₃ program the Vgs_(M24) ₁₃ that biases the cascoded FETs M25 ₁₃to M29 ₁₃ which provides sufficient drain-to-source voltages (V_(DS))head-room and substantially equalizes the V_(DS) between M31 ₁₃ and M32₁₃ for better current matching and also to maintain their operation inthe saturation regions. Also, to enhance the dynamic response of iTv₁₃and vTi₁₃, a constant current Ij₁₃ is added to keep the diode connectedM31 ₁₃ constantly alive during D_(i)I_(o) sMACiDAC's zero and full scaletransitions, and accordingly an substantially equal current Ij′₁₃ issubtracted from drain terminal of M32 ₁₃ to keep the mirror balanced.

Bear in mind that for better dynamic response and substantiallyequalization between the operating voltages at the I_(o) ⁻ and I_(o) ⁺ports of the DACw₁₃, DACx₁₃, and DACy₁₃, their I_(o) ⁻ ports can becoupled with drain terminal of M30 ₁₃ (also coupled with source terminalof M25 ₁₃), while a current source (e.g., Ij″₁₃ not shown in FIG. 13)can be coupled with gate terminal of M30 ₁₃ (also coupled with drainterminal of M25 ₁₃).

In summary, the embodiment illustrated in FIG. 13 of a mixed-mode scalarmultiply-accumulate (D_(i)I_(o) sMACiDAC) circuit that processes signalsin current-mode utilizing iDACs has the following benefits:

First, the disclosed D_(i)I_(o) sMACiDAC utilizing plurality of iDACs(along with CCVS and VCCS) whose outputs are summed in current-mode andfed onto the reference input terminal of a scalar iDAC saves area andlowers cost, and improved performance with faster dynamic response. Thisis in part due to the efficacy in performing the distributive propertyin current-mode, wherein multiplying the sum of two or more addends by anumber will give the same result as multiplying each addend individuallyby the number and then adding the products together. Summation incurrent-mode is accomplished by simply coupling plurality of addends(i.e., coupling the output of plurality of iDACs together), and feedingthe said summation to another scalar iDAC's reference input. This willresult in multiplying each addend individually by the scalar number andthen adding the products together, which is fast since signals areprocessed in current-mode.

Second, utilizing the floating iDAC method disclosed in FIG. 1 section1, saves area and reduces FETs sizes carrying lower capacitances in theiDAC's current reference network which in turn lowers the cost, reducesthe size, and improves the transient response of the D_(i)I_(o) sMACiDACthat utilizes such iDACs.

Third, as noted earlier, the disclosed D_(i)I_(o) sMACiDAC utilizingiDACs that operate in current-mode is inherently fast.

Fourth, voltage swings in current-mode signal processing are small,which enables operating the disclosed D_(i)I_(o) sMACiDAC with lowerpower supply voltage and retain the speed and dynamic rage benefits.

Fifth, operating at low supply voltage reduces power consumption of thedisclosed D_(i)I_(o) sMACiDAC. Additionally, the flexibility to run theCMOSFETs in subthreshold enables a iDAC that are utilized in D_(i)I_(o)sMACiDAC to operate with ultra-low currents, even lower power supplies,and ultra-low power consumption suitable for mobile applications,especially in AI and ML applications that may require numerous ultra-lowpower and low power supply iDACs for computation.

Sixth, the disclosed D_(i)I_(o) sMACiDAC utilizing iDAC for signalprocessing such as addition or subtraction operations, in current mode,take small area and can be performed fast.

Seventh, by substantially equalizing the terminal voltages at I_(o) ⁺and I_(o) ⁻ ports of plurality of iDACs as well as the I_(o) ⁺ and I_(o)⁻ ports of scalar iDACs utilized in the disclosed D_(i)I_(o) sMACiDAC,improves the D_(i)I_(o) sMACiDAC's transient response and glitch isreduced during on-to-off D_(i)I_(o) sMACiDAC's digital input codetransitions.

Eight, there are no passive devices in the disclosed D_(i)I_(o) sMACiDACof FIG. 13, and as such there is no need for resistors or capacitors,which reduces manufacturing size and cost.

Ninth, the precision of the disclosed D_(i)I_(o) sMACiDAC can beimproved by improving the accuracy of iDACs (for example) by segmentingthe iDAC's reference current transfer-function (along with digitalbinary-to-thermometer logic decoding of iDAC's digital input code).

Tenth, the disclosed D_(i)I_(o) sMACiDAC of FIG. 13 can utilize lowerresolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplicationfunction, which occupy smaller areas, but can still deliver higheraccuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. Forexample, higher than 3 of 5 bits of accuracy for iDACs is attainable instandard CMOS fabrication due to (8-bits of accuracy or ±0.4%) matchingthat is achievable between the iDAC's binary weighted current sources orsegmented current sources. As such, the disclosed D_(i)I_(o) sMACiDACcan utilize low resolution iDACs that occupy small areas but stillachieve higher accuracy multiply-accumulate performance at lower cost.

Eleventh, glitch is lower during code transitions in D_(i)I_(o) sMACiDACbecause floating iDACs utilized in D_(i)I_(o) sMACiDAC can be madesmaller given that their input-to-output transfer function networkutilizes smaller devices that carry smaller capacitances, which injectfewer analog glitches to the output of the D_(i)I_(o) sMACiDAC duringdigital input code transitions.

Twelfth, dynamic power consumption is lower because the D_(i)I_(o)sMACiDAC utilizes floating iDAC that have smaller sized FETs (in theinput-to-output transfer function network) which would consume lessdynamic current to drive smaller FET devices during digital input codetransitions.

Thirteenths, the D_(i)I_(o) sMACiDAC that utilizes floating iDAC can bearranged free of clock, suitable for asynchronous (clock free)computation.

Fourteenth, the D_(i)I_(o) sMACiDAC that utilizes same type of MOSFETcurrent sources and MOSFET switches in the respective floating iDACs,which are symmetric, matched, and scaled. Such arrangement facilitatesdevice parameters to track each other over process-temperature-operationconditions variations. Accordingly, the D_(i)I_(o) sMACiDAC'stemperature coefficient, power supply coefficient, and AC power supplyrejection performance can be enhanced.

Fifteenth, while digital computation is generally accurate but it may beexcessively power hungry. Current-mode analog and mixed-signalcomputation that is disclosed here can be approximate but signalprocessing can be accomplished asynchronously and power consumption canbe lower. Moreover, analog current errors here generally result indegradation but (not total failures) of analog computation, whichprovides the end-application with approximate results to work withinstead of experiencing failed results.

Sixteenth, the embodiment disclosed here is not restricted by FETshaving to operate either in saturation (high-currents) or subthreshold(low currents). For example, some analog signal processing units rely onoperating transistors in the subthreshold regions which restricts thedynamic range of analog signal processing circuits to low currentsignals. Also, some other analog signal processing units rely onoperating transistors with high currents in the saturation regions whichrestricts the dynamic range of analog signal processing circuits tohigher current signals.

Seventeenth, utilizing plurality of iDACs, whose outputs are summed,would attenuate the statistical contribution of the cumulative iDAC'srandom errors (such as random noise, offset, mismatches, linearity,gain, drift, etc.) at the summing node where the iDAC's current outputsare coupled. The statistical contribution of such cumulative iDAC'srandom errors, at the summing node, is the square root of the sum of thesquares of such random error terms.

Section 14—Description of FIG. 14

FIG. 14 is a simplified functional block diagram illustrating anotherembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signalcurrent-mode digital-input to analog-current-output (D_(i)I_(o)) scalarmultiply-accumulate (SMAC) circuit utilizing current-modedigital-to-analog-converters (iDAC).

The disclosed embodiment of D_(i)I_(o) sMACiDAC in FIG. 14 also utilizesthe a multiplication property, wherein multiplying the sum of two ormore (plurality of) addends by a (scalar) number will give the sameresult as multiplying each addend individually by the number and thenadding the products together. To accomplish this objective, thedisclosed circuit of FIG. 14 utilizes a scalar iDACs that receives adigital input word (s_(D)) and generates an analog current (s_(A)).Concurrently, a plurality of iDACs receive a respective plurality ofdigital input words (p_(D)). The s_(A) is replicated onto plurality ofs_(A)s that are supplied to a plurality reference inputs of theplurality of iDACs. The outputs of the plurality of iDACs are coupletogether to generate a summation current signal, which is the product ofs_(A) (which represent the analog value of s_(D)) multiplied by the sumof a plurality p_(Ai) (which represent a plurality of respective analogvalue of the respective plurality of p_(D)) or

${s_{A} \times {\sum\limits_{m = 1}^{n}p_{Ai}}} = {\sum\limits_{m = 1}^{n}{s_{A} \times {p_{Ai}.}}}$

To further describe the disclosed D_(i)I_(o) sMACiDAC circuit embodimentof FIG. 14, let the FET's W/L factors a=b=c=d=e=1. For an A_(Rz) feedingthe reference input of scalar DACz₁₄, its output signal

$A_{z} = {A_{Rz} \times {\sum\limits_{l = 1}^{z}{D_{l}/{2^{l}.}}}}$Similarly

${A_{w} = {A_{Rw} \times {\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}}}},{A_{x} = {A_{Rx} \times {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}}}},$and

$A_{y} = {A_{Ry} \times {\sum\limits_{k = 1}^{y}{D_{k}/{2^{k}.}}}}$By replicating and feeding substantially equal values of A_(z) onto thereference inputs of a plurality (e.g., 3 channels) of floating iDACs,namely DACw₁₄, DACx₁₄, and DACy₁₄, then:A_(Rw)=A_(Rx)=A_(Ry)=A_(z)=A_(Rz)×Σ_(l=1) ^(z)D_(l)/2^(l). Therefore,

${\left( {A_{Rz} \times {\sum\limits_{l = 1}^{z}{D_{l}/2^{l}}}} \right) \times {\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}}};{\left( {A_{Rz} \times {\sum\limits_{l = 1}^{z}{D_{l}/2^{l}}}} \right) \times {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}}};$$\left( {A_{Rz} \times {\sum\limits_{l = 1}^{z}{D_{l}/2^{l}}}} \right) \times {\sum\limits_{k = 1}^{y}{D_{k}/{2^{k}.}}}$

Therefore, the disclosed D_(i)I_(o) sMACiDAC output current signal whichis the summation of w, x, and y—iDAC's outputs is thus:

${A_{w} + A_{x} + A_{y}} = {A_{Rz} \times {\sum\limits_{l = 1}^{z}{{D_{l}/2^{l}} \times {\left( {{\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}} + {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}} + {\sum\limits_{k = 1}^{y}{D_{k}/2^{k}}}} \right).}}}}$Therefore,

${{A_{o}/A_{R}} = {\left\lbrack \left( {{\sum\limits_{i = 1}^{w}{D_{i}/2^{i}}} + {\sum\limits_{j = 1}^{x}{D_{j}/2^{j}}} + {\sum\limits_{k = 1}^{y}{D_{k}/2^{k}}}} \right) \right\rbrack \times {\sum\limits_{l = 1}^{z}{D_{l}/2^{l}}}}},$which can be mapped in the analog domain asA_(o)/A_(R)=(A_(w)+A_(x)+A_(y))×A_(z) representing multiplying scalar zby the accumulation of w, x, and y.

Note that in FIG. 14, the scalar DACz₁₄ and plurality of iDACs (e.g.,for 3-channels DACw₁₄, DACx₁₄, and DACy₁₄) are shown with 3-bit ofresolution with i=j=k=l=3. In FIG. 14's illustration of D_(i)I_(o)sMACiDAC embodiment with 3-bits of resolution and 3 channels is forillustrative clarity of description, but not as a limitation of thisdisclosure. Resolution of iDACs can be up to 16-bits, and the pluralityof iDACs can be a sea of iDACs and for example 1000 channels.

Here, a more detailed description of embodiment of the D_(i)I_(o)sMACiDAC's circuit illustrated in FIG. 14 is provided. The referencecurrent I1 ₁₄=I_(r′) is applied to a diode connected M17 ₁₄ whoseVgs_(M17) ₁₄ biases the binary weighted current source network of thescalar DACz₁₄. Let e=1 for this illustration. Consider that M18 ₁₄ andI2 ₁₄ program the Vgs_(M18) ₁₄ that biases the cascoded FETs is intendedto increase (accuracy and) the output impedance of DACz₁₄'s currentsource network.

A DACz₁₄ receives a digital word Dz₁₄, and generates an analog outputcurrent Az₁₄, wherein Vgs_(M17) ₁₄ biases M23 ₁₄, M24 ₁₄, and M25 ₁₄(according to their respective width-over-length or W/L scales e.x, 1x,2x, 4×) which programs the DACz₁₄'s binary weighted currents as a ratioof the I1 ₁₄=I_(r′). The DACz₁₄'s current switches S10 ₁₄, S11 ₁₄, andS12 ₁₄ steer the respective M23 ₁₄, M24 ₁₄, and M25 ₁₄ currents toeither a diode connected M5 ₁₄ (which is coupled with the DACz₁₄'s I_(o)⁻ port) or the DACz₁₄'s I_(o) ⁺ port (for Az₁₄ signal) in accordancewith the polarity of the Dz₁₄ bits. As it would be clear to one skilledin the art, for example, when Dz₁₄'s MSB in on (high-state), then S10 ₁₄steers M23 ₁₄'s current (through the cascoded FET M19 ₁₄) onto theDACz₁₄'s I_(o) ⁺ port (carrying the an analog output current Az₁₄).Conversely, when Dz₁₄'s MSB in off (low-state), then S10 ₁₄ steers M23₁₄'s current (through the cascoded FET M19 ₁₄) onto the DACz₁₄'s I_(o) ⁻port and onto the diode connected M5 ₁₄. Also, notice that for e=1, theDACz₁₄ full-scale output is I1 ₄ (4+2+1)=7I_(r′).

As noted earlier, Az₁₄ (which is the current outputs of the DACz₁₄) isreplicated and fed onto the reference input terminals of DACw₁₄, DACx₁₄,and DACy₁₄. In the embodiment of FIGS. 15 and 14, proportionalreplication of Az₁₄ is effectuated via feeding Az₁₄ onto acurrent-controlled-voltage source (CCVS) with a gain of 1/g, whoseoutput voltage can then feed plurality of (e.g., 3)voltage-controlled-current-sources (VCCSs) with their gains proportionalto g. The plurality of outputs of the VCCSs can then feed the referenceinput terminals of a plurality of iDACs (e.g., DACw₁₄, DACx₁₄, andDACy₁₄).

More specifically, in FIG. 14, the CCVS and VCCSs are implemented byfeeding Az₁₄ current onto a diode connected M4 ₁₄ whose current isscaled and mirrored through M1 ₁₄, M2 ₁₄, and M3 ₁₄. For descriptiveclarity, let M1 ₁₄ to M4 ₁₄'s W/L factors a=b=c=d=1 (which programs thegains of CCVS and VCCS). As described in the floating iDAC of FIG. 2section 2, M1 ₁₄, M2 ₁₄, and M3 ₁₄ supply the reference current signalfor the three floating iDACs here: DACw₁₄, DACx₁₄, and DACy₁₄. Also,bias current I2 ₁₄ and a diode connected M6 ₁₄ program Vgs_(M614) whichbiases the respective DACw₁₄, DACx₁₄, and DACy₁₄'s binary weightedcurrent networks comprising of M7 ₁₄M9 ₁₄, M10 ₁₄-M12 ₁₄, and M13 ₁₄-M15₁₄, respectively.

A DACw₁₄ receives a digital word Dw₁₄ at its digital input port,receives a reference current signal that is a proportional replica ofAz₁₄ through a current mirror (M4 ₁₄, M1 ₁₄) and generates an analogoutput current signal Aw₁₄×Az₁₄. As noted earlier, floating DACw₁₄'sreference current is proportional to Az₁₄ that (through M1 ₁₄) isbinarily distributed between M7 ₁₄, M8 ₁₄, and M9 ₁₄, according to theirrespective width-over-length or W/L scales 1x, 2x, 4x. The DACw₁₄'scurrent switches S1 ₁₄, S2 ₁₄, and S3 ₁₄ steer the respective M7 ₁₄, M8₁₄, and M9 ₁₄ currents to either a diode connected M26 ₁₄ (which iscoupled with the DACw₁₄'s I_(o) ⁻ port) or the DACw₁₄'s I_(o) ⁺ port(carrying a Aw₁₄×Az₁₄ current signal) in accordance with the polarity ofthe Dw₁₄ bits.

A DACx₁₃ receives a digital word Dx₁₄ at its digital input port,receives a reference current signal that is a proportional replica ofAz₁₄ through a current mirror (M4 ₁₄, M2 ₁₄) and generates an analogoutput current signal Ax₁₄×Az₁₄. As noted earlier, floating DACx₁₄'sreference current is proportional to Az₁₄ that (through M2 ₁₄) isbinarily distributed between M10 ₁₄, M11 ₁₄, and M12 ₁₄, according totheir respective width-over-length or W/L scales 1x, 2x, 4x. TheDACx₁₄'s current switches S4 ₁₄, S5 ₁₄, and S6 ₁₄ steer the respectiveM10 ₁₄, M11 ₁₄, and M12 ₁₄ currents to either a diode connected M26 ₁₄(which is coupled with the DACx₁₄'s I_(o) ⁻ port) or the DACx₁₄'s I_(o)⁺ port (carrying a Ax₁₄×Az₁₄ current signal) in accordance with thepolarity of the Dx₁₄ bits.

A DACy₁₃ receives a digital word Dy₁₄ at its digital input port,receives a reference current signal that is a proportional replica ofAz₁₄ through a current mirror (M4 ₁₄, M3 ₁₄) and generates an analogoutput current signal Ay₁₄×Az₁₄. As noted earlier, floating DACy₁₄'sreference current is proportional to Az₁₄ that (through M3 ₁₄) isbinarily distributed between M13 ₁₄, M14 ₁₄, and M15 ₁₄, according totheir respective width-over-length or W/L scales 1x, 2x, 4x. TheDACy₁₄'s current switches S7 ₁₄, S8 ₁₄, and S9 ₁₄ steer the respectiveM13 ₁₄, M14 ₁₄, and M15 ₁₄ currents to either a diode connected M26 ₁₄(which is coupled with the DACy₁₄'s I_(o) ⁻ port) or the DACy₁₄'s I_(o)⁺ port (carrying a Ay₁₄×Az₁₄ current signal) in accordance with thepolarity of the Dy₁₄ bits.

As indicated earlier, DACz₁₄'s full scale output current is 7I1₄=7I_(r′), and as such the DACw₁₄, DACx₁₄, and DACy₁₄ full scale can beprogrammed to 7I_(r′) with a=b=c=d=e=1. In this case, the summation ofDACw₁₄, DACx₁₄, and DACy₁₄ full-scale output current or summation ofAw₁₄×Az₁₄+Ax₁₄×Az₁₄+Ay₁₄×Az₁₄ would compute to 3×7I_(r′)=21I_(r′). Theoutput of sMACiDAC can be represented in the analog domain andproportional to 21I_(r′)=A_(R″): A_(o)/A_(R″)=(A_(w)+A_(x)+A_(y))×A_(z).

As stated earlier, M6 ₁₄ and I2 ₁₄ program the Vgs_(M6) ₁₄ that biasesthe floating current sources of DACw₁₄, DACx₁₄, and DACy₁₄ as well asprovide sufficient drain-to-source voltages (V_(DS)) head-room andsubstantially equalizes the V_(DS) between M1 ₁₄ and M3 ₁₄ for bettercurrent matching and also to maintain their operation in the saturationregions. Also, to enhance the dynamic response D_(i)I_(o) sMACiDAC aconstant current Ij₁₄ is added to keep the diode connected M4 ₁₄ aliveduring DACw₁₄'s zero and full scale transitions, and accordingly aproportional current Ij′₁₄ (e.g., 3×Ij₁₄) is subtracted from the currentoutput terminal of D_(i)I_(o) sMACiDAC.

In summary, the embodiment of the D_(i)I_(o) sMACiDAC circuitillustrated in FIG. 14 that processes signals in current-mode byutilizing iDACs has the following benefits:

First, the disclosed D_(i)I_(o) sMACiDAC utilizing a current mode scalariDACs whose output is copied and fed onto the reference input terminalsof plurality of iDAC saves area and lowers cost, and improvedperformance with faster dynamic response, in part for its efficacy inperforming summation in current-mode that can be accomplished by simplycoupling plurality of current signals.

Second, utilizing the floating iDAC method disclosed in FIG. 1 section1, saves area and reduces FETs sizes (which lower capacitance) in theiDAC's current reference network which in turn lowers the cost, reducesthe size, and improves the transient response of the D_(i)I_(o) sMACiDACthat utilizes such iDACs.

Third, as noted earlier, the disclosed D_(i)I_(o) sMACiDAC utilizingiDACs that operate in current-mode is inherently fast.

Fourth, voltage swings in current-mode signal processing are small,which enables operating the disclosed D_(i)I_(o) sMACiDAC of FIG. 14with lower power supply voltage and retain the speed and dynamic ragebenefits.

Fifth, operating at low supply voltage reduces power consumption of thedisclosed D_(i)I_(o) sMACiDAC. Additionally, the flexibility to run theCMOSFETs in subthreshold enables a iDAC that are utilized in D_(i)I_(o)sMACiDAC to operate with ultra-low currents, even lower power supplies,and ultra-low power consumption suitable for mobile applications,especially in AI and ML applications that may require numerous ultra-lowpower and low power supply iDACs for computation.

Sixth, the disclosed D_(i)I_(o) sMACiDAC utilizing iDAC for signalprocessing such as addition or subtraction functions (in current mode)take small area and can be performed fast.

Seventh, by substantially equalizing the terminal voltages at I_(o) ⁺and I_(o) ⁻ ports of plurality of iDACs as well as the I_(o) ⁺ and I_(o)⁻ ports of scalar iDACs utilized in the disclosed D_(i)I_(o) sMACiDAC,improves the D_(i)I_(o) sMACiDAC's transient response and glitch isreduced during on-and-off D_(i)I_(o) sMACiDAC's digital input codetransitions.

Eight, there are no passive devices in the disclosed D_(i)I_(o) sMACiDACof FIG. 14, and as such there is no need for resistors or capacitors,which reduces manufacturing size and cost.

Ninth, the precision of the disclosed D_(i)I_(o) sMACiDAC can beimproved by improving the accuracy of iDACs (for example) by segmentingthe iDAC's reference current transfer-function (along with digitalbinary-to-thermometer logic decoding of iDAC's digital input code).

Tenth, the disclosed D_(i)I_(o) sMACiDAC of FIG. 14 can utilize lowerresolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplicationfunction, which occupy smaller areas, but can still deliver higheraccuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. Forexample, higher than 3 of 5 bits of accuracy for iDACs is attainable instandard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%)matching that is achievable between the iDAC's binary weighted currentsources or segmented current sources. As such, the disclosed D_(i)I_(o)sMACiDAC can utilize low resolution iDACs that occupy small areas butstill achieve higher accuracy multiply-accumulate performance at lowercost.

Eleventh, glitch is lower during code transitions in D_(i)I_(o) sMACiDACbecause floating iDACs utilized in D_(i)I_(o) sMACiDAC can be madesmaller given that their input-to-output transfer function networkutilizes smaller devices that carry smaller capacitances, which injectfewer analog glitches to the output of the D_(i)I_(o) sMACiDAC duringdigital input code transitions.

Twelfth, dynamic power consumption is lower because the D_(i)I_(o)sMACiDAC utilizes floating iDAC that have smaller sized FETs (in theinput-to-output transfer function network) which would consume lessdynamic current to drive smaller FET devices during digital input codetransitions.

Thirteenths, the D_(i)I_(o) sMACiDAC that utilizes floating iDAC can bearranged free of clock, suitable for asynchronous (clock free)computation.

Fourteenth, the D_(i)I_(o) sMACiDAC that utilizes same type of MOSFETcurrent sources and MOSFET switches in the respective floating iDACs,which are symmetric, matched, and scaled. Such arrangement facilitatesdevice parameters to track each other over process, temperature, andoperating conditions variations. Accordingly, the D_(i)I_(o) sMACiDAC'stemperature coefficient, power supply coefficient, and AC power supplyrejection performance can be enhanced.

Fifteenth, while digital computation is generally accurate but it may beexcessively power hungry. Current-mode analog and mixed-signalcomputation that is disclosed here can be approximate but signalprocessing can be accomplished asynchronously and power consumption canbe lower. Moreover, analog current errors here generally may result indegradation but (not total failures) of analog computation, whichprovides the end-application with approximate results to work withinstead of experiencing failed results.

Sixteenth, the embodiment disclosed here is not restricted by FETshaving to operate either in saturation (high-currents) or subthreshold(low currents). For example, some analog signal processing units rely onoperating transistors in the subthreshold regions which restricts thedynamic range of analog signal processing circuits to low currentsignals. Also, some other analog signal processing units rely onoperating transistors with high currents in the saturation regions whichrestricts the dynamic range of analog signal processing circuits tohigher current signals.

Seventeenth, utilizing plurality of iDACs, whose outputs are summed,would attenuate the statistical contribution of the cumulative iDAC'srandom errors (such as random noise, offset, mismatches, linearity,gain, drift, etc.) at the summing node where the iDAC's current outputsare coupled. The statistical contribution of such cumulative iDAC'srandom errors, at the summing node, is the square root of the sum of thesquares of such random error terms.

Section 15—Description of FIG. 15

FIG. 15 is a simplified functional block diagram illustrating anotherembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signalcurrent-mode digital-input to digital-output (D_(i)D_(o)) scalarmultiply-accumulate (sMAC) plus bias circuit utilizing current-modedigital-to-analog-converters (iDAC) and current-mode analog-to-digitalconverters (iADC).

Utilizing current-mode data-converters, the D_(i)D_(o) sMACiDACembodiment disclosed in FIG. 15, first multiplies a scalar currentsignal by a respective plurality of current signals, whose products aresummed together in current-mode and added to a bias current signal togenerate a final summation signal. This final summation current signalis digitized via a current-mode analog-to-digital-converter (iADC). FIG.15 disclosure performs the multiply-accumulate function by utilizinganalog and mixed-signal signal processing in current-mode, by arrangingdata-converters to leverage the distributive property of multiplication,to save area and improve performance in multiply-accumulate functionsneeded in AI and ML applications. As such, the embodiment disclosed inFIG. 15, performs the function of

${\sum\limits_{i = 1}^{p}\left( {{s \times W_{i}} + b} \right)},$where s is scalar current signal (e.g., s can be programmed by iDACz₁₅),W_(i) is plurality of weight current signals with p as pluralities ofchannels (e.g., p=3 of W_(i) current signals can be programmed byiDACw₁₅, iDACx₁₅, and iDACy₁₅, respectively), and b is bias currentsignal (e.g., b current signal can be programmed by DACb_(is)). Asindicated in prior sections, the illustration of FIG. 15 depicts(plurality) p=3 channels for clarity of description, but n can be a seaof channels depending on application and as many as 1000.

In FIG. 15, a scalar iDACz₁₅ is supplied with a reference current signalI1 ₁₅ at its zR₁₅ port, receives a z-bits wide digital input word Dz₁₅,and accordingly iDACz₁₅ generates an analog output current signal Az₁₅.

The Az₁₅ current is inputted to a current-controlled-voltage-sourceCCVS₁₅'s current input port, whose gain is programmed to g₁₅. TheCCVS₁₅'s voltage output port is coupled with a plurality ofvoltage-controlled-current sources VCCSs₁₅, which in the FIG. 15illustration are 3-channels VCCS1 ₁₅, VCCS2 ₁₅, and VCCS3 ₁₅ but couldbe more depending on the application requirement. The gains of VCCS1 ₁₅,VCCS2 ₁₅, and VCCS3 ₁₅ can be programmed to a/g₁₅, b/g₁₅, and c/g₁₅,respectively. It is of note that the CCVS and plurality of VCCS can beimplemented with current mirrors, such as the one illustrated in FIG. 14(e.g., M4 ₁₄, M1 ₁₄, M2 ₁₄, and M3 ₁₄). A plurality of iDAC's referenceports are supplied with a respective plurality of proportionalreplicates of scalar iDAC's output current signal as follows:

An iDACw₁₅ is supplied with the VCCS1 ₁₅'s output current (a×Az₁₅) atiDACw₁₅'s reference port wR₁₅ port. The iDACw₁₅ receives a w-bits widedigital input word Dw₁₅, and accordingly iDACw₁₅ generates an analogoutput current signal a×Az₁₅×Aw₁₅.

An iDACx₁₅ is supplied with the VCCS2 ₁₅'s output current (b×Az₁₅) atiDACx₁₅'s reference port xR₁₅ port. An iDACx₁₅ receives a v-bits widedigital input word Dx₁₅, and accordingly iDACx₁₅ generates an analogoutput current signal b×Az₁₅×Ax₁₅.

An iDACy₁₅ is supplied with the VCCS3 ₁₅'s output current (c×Az₁₅) atiDACy₁₅'s reference port yR₁₅ port. An iDACy₁₅ receives a y-bits widedigital input word Dy₁₅, and accordingly iDACy₁₅ generates an analogoutput current signal c×A_(z15)×Ay₁₅.

A bias iDACb₁₅ is supplied with a reference current signal I2 ₁₅ at itsbR₁₅ port, receives a b-bits wide digital input word Db₁₅, andaccordingly iDACb₁₅ generates an analog output current signal Ab₁₅.

The current outputs of iDACw₁₅, iDACx₁₅, iDACy₁₅, and iDACb₁₅ arecoupled together to generate a summation current signal ofa×Az₁₅×Aw₁₅+b×Az₁₅×Ax₁₅+c×Az₁₅×Ay₁₅+Ab₁₅=Az₁₅×(a×A_(w15)+b×Ax₁₅+c×Ay₁₅)+Ab₁₅.This summation current signal is concurrently fed onto a current inputport of iADC₁₅ which is a current-mode analog-to-digital-converter(iADC), which generates a o-bits wide digital output word Do₁₅ which isthe digital representation of the D_(i)D_(o) iMACiDAC output signalAz₁₅×(a×Aw₁₅+b×Ax₁₅+c×Ay₁₅)+Ab₁₅.

In summary, the D_(i)D_(o) sMACiDAC embodiment illustrated in FIG. 15that processes signals in current-mode utilizing iDACs has the followingbenefits:

First, the disclosed D_(i)I_(o) sMACiDAC utilizing plurality ofcurrent-mode iDACs whose certain outputs can be coupled together andbiased (in current mode) saves area (lower cost) and improvedperformance (faster dynamic response), in part for its efficacy inperforming summation in current-mode that can be accomplished by simplycoupling plurality of current signals.

Second, standard iDACs or factorized or floating iDACs methods(described earlier in the disclosure) can be utilized, which saves areaand reduces FETs sizes with lower capacitances in the iDAC's currentreference network, which in turn lowers the cost, reduces the size, andimproves the transient response of the D_(i)D_(o) sMACiDAC that utilizessuch iDACs.

Third, as noted earlier, operating in current mode has the followingbenefits for the disclosed D_(i)D_(o) sMACiDAC: (a) current mode isinherently fast, (b) voltage swings in current-mode signal processingare small, which enables operating with lower power supply voltage andoperating at low supply voltages facilitates reducing power consumption,(c) current-mode signal processing such as addition or subtractionfunctions take small area and can be performed fast.

Fourth, there are no passive devices in the disclosed D_(i)D_(o)sMACiDAC of FIG. 15, and as such there is no need for resistors orcapacitors, which reduces manufacturing size and cost.

Fifth, the precision of the disclosed D_(i)D_(o) sMACiDAC can beimproved by improving the accuracy of iDACs (for example) by segmentingthe iDAC's reference current transfer-function (along with digitalbinary-to-thermometer logic decoding of iDAC's digital input code).

Sixth, the disclosed D_(i)D_(o) sMACiDAC of FIG. 15 can utilize lowerresolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplicationfunction, which occupy smaller areas, but can still deliver higheraccuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. Forexample, higher than 3 of 5 bits of accuracy for iDACs is attainable instandard CMOS fabrication factories due to (8-bits of accuracy or±0.4%)) matching that is achievable between the iDAC's binary weightedcurrent sources or segmented current sources. As such, the disclosedD_(i)D_(o) sMACiDAC can utilize low resolution iDACs that occupy smallareas but still achieve higher accuracy multiply-accumulate performanceat lower cost.

Seventh, dynamic power consumption is lower because the D_(i)D_(o)sMACiDAC by utilizing floating, factorized, or combination of floatingand factorized iDACs which have smaller sized FETs (in theinput-to-output transfer function network) which would consume lessdynamic current to drive smaller FET devices during digital input codetransitions.

Eight, the D_(i)D_(o) sMACiDAC that utilizes floating iDAC can bearranged free of clock, suitable for asynchronous (clock free)computation.

Ninth, the D_(i)D_(o) sMACiDAC that utilizes same type of MOSFET currentsources and MOSFET switches in the respective floating, factorized, orcombination of floating and factorized iDACs, which are symmetric,matched, and scaled. Such arrangement facilitates device parameters totrack each other over process, temperature, operating conditionvariations. Accordingly, the D_(i)D_(o) sMACiDAC's temperaturecoefficient, power supply coefficient, and AC power supply rejectionperformance can be enhanced.

Tenth, while digital computation is generally accurate but it may beexcessively power hungry. Current-mode analog and mixed-signalcomputation that is disclosed here can be approximate but signalprocessing can be accomplished asynchronously and power consumption canbe lower. Moreover, analog current errors here generally may result indegradation but (not total failures) of analog computation, whichprovides the end-application with approximate results to work withinstead of experiencing failed results.

Eleventh, utilizing plurality of iDACs, whose outputs are summed, wouldattenuate the statistical contribution of the cumulative iDAC's randomerrors (such as random noise, offset, mismatches, linearity, gain,drift, etc.) at the summing node where the iDAC's current outputs arecoupled. The statistical contribution of such cumulative iDAC's randomerrors, at the summing node, is the square root of the sum of thesquares of such random error terms.

Section 16—Description of FIG. 16

FIG. 16 is a simplified functional block diagram illustrating anotherembodiment of a mixed-signal current-mode scalar multiply-accumulate(sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signalcurrent-mode digital-input to digital-output (D_(i)D_(o)) scalarmultiply-accumulate (sMAC) plus bias circuit utilizing current-modedigital-to-analog-converters (iDAC) and current-mode analog-to-digitalconverters (iADC).

Utilizing current-mode data-converters, the D_(i)D_(o) sMACiDACembodiment disclosed in FIG. 16, first a plurality of current signalsare summed together, wherein the said summation current signal ismultiplied by a scalar current signal, whose products are summedtogether in current-mode and added to a bias current signal to generatea final summation signal. This final summation current signal isdigitized via a current-mode analog-to-digital-converter (iADC). FIG. 16disclosure performs the multiply-accumulate function by utilizing analogand mixed-signal signal processing in current-mode, by arrangingdata-converters to leverage the distributive property of multiplication,to save area and improve performance in multiply-accumulate functionsneeded in AI and ML applications. As such, the embodiment disclosed inFIG. 16, performs the function of

${\sum\limits_{i = 1}^{p}\left( {{s \times W_{i}} + b} \right)},$where s is scalar current signal (e.g., s can be programmed by iDACz₁₆),W_(i) is plurality of weight current signals with p as pluralities ofchannels (e.g., p=3 of W_(i) current signals can be programmed byiDACw₁₆, iDACx₁₆, and iDACy₁₆, respectively), and b is bias currentsignal (e.g., b current signal can be programmed by DACb₁₆). Asindicated in prior sections, the illustration of FIG. 16 depicts(plurality) p=3 channels for clarity of description, but n can be a seaof channels depending on application and as many as 1000.

In FIG. 16, a plurality of iDAC's reference ports are supplied with arespective plurality of current reference signals, wherein the pluralityof iDACs generate a plurality of output current signals, which arecoupled together to generate a summation current signal as follows: AniDACw₁₆ is supplied with the I1 ₁₆ reference current at iDACw₁₆'sreference port wR₁₆ port. The iDACw₁₆ receives a w-bits wide digitalinput word Dw₁₆, and accordingly iDACw₁₆ generates an analog outputcurrent signal Aw₁₆. An iDACx₁₆ is supplied with the I2 ₁₆ referencecurrent at iDACx₁₆'s reference port xR₁₆ port. The iDACx₁₆ receives av-bits wide digital input word Dx_(m), and accordingly iDACx₁₆ generatesan analog output current signal Ax₁₆. An iDACy₁₆ is supplied with the I3₁₆ reference current at iDACy₁₆'s reference port yR₁₆ port. The iDACy₁₆receives a y-bits wide digital input word Dy₁₆, and accordingly iDACy₁₆generates an analog output current signal Ay₁₆. The output currents ofthe iDACw₁₆, iDACx₁₆, and iDACy₁₆ are coupled together to generate asummation current represented by Aw₁₆+Ay₁₆+Ax₁₆ which is fed onto aninput port of current-controlled-voltage source CCVS₁₆ (which a gain ofg₁₆) whose output is coupled with an input of avoltage-controlled-current-source VCCS₁₆ (which a gain of a/g₁₆).Considering the net-gain of g₁₆×1/g₁₆=a attributed to CCVS₁₆ and VCCS₁₆combination, output current representing (Aw₁₆+Ay₁₆+Ax₁₆)×a is generatedat the output port of VCCS₁₆.

The output current of VCCS₁₆ is concurrently fed onto zR₁₆ which is areference input terminal of a scalar iDACz₁₆. The iDACz₁₆ receives az-bits wide digital input word Dz₁₆, and accordingly iDACz₁₆ generatesan analog output current signal that represents a×Az₁₆×(Aw₁₆+Ay₁₆+Ax₁₆).

Also concurrently, a bias iDACb₁₆ is supplied with a reference currentsignal I4 ₁₆ at its bR₁₆ port, receives a b-bits wide digital input wordDb₁₆, and accordingly iDACb₁₆ generates an analog output current signalAb₁₆.

The output of iDACz₁₆ and output of iDACb₁₆ are coupled together togenerate a final summation current signal representinga×Az₁₆×(Aw₁₆+Ay₁₆+Ax₁₆)+Ab₁₆. This final summation current signal isconcurrently fed onto a current input port of iADC₁₆ which is acurrent-mode analog-to-digital-converter (iADC), which generates ao-bits wide digital output word Do₁₆ which is the digital representationof the D_(i)D_(o) iMACiDAC output signal a×Az₁₆×(Aw₁₆+Ay₁₆+Ax₁₆)+Ab₁₆.

Bear in mind that FIG. 13 can be a circuit embodiment of the functionalblock diagram illustrating the embodiment of D_(i)D_(o) sMACiDAC circuitof FIG. 16, excluding the iDACb₁₆ and iADC₁₆. Also, keep in mind thatsimilar to the circuit embodiment illustrated in FIG. 13, the CCVS₁₆ andVCCS₁₆ combination in FIG. 16 can correspond to the iTv₁₃ and vTi₁₃combination in FIG. 13 (comprising of M26 ₁₃, M27 ₁₃, M31 ₁₃, and M32 ₁₃and Ij₁₃, Ij′₁₃).

In summary, the embodiment illustrated in FIG. 16 of a mixed-mode scalarmultiply-accumulate (D_(i)D_(o) sMACiDAC) circuit that processes signalsin current-mode utilizing iDACs has the following benefits:

First, the disclosed D_(i)I_(o) sMACiDAC utilizing plurality ofcurrent-mode iDACs whose certain outputs can be coupled together andbiased in current mode, which saves area and lowers cost, and improvedperformance with faster dynamic response, in part for its efficacy inperforming summation in current-mode that can be accomplished by simplycoupling plurality of current signals.

Second, standard iDACs or factorized or floating iDACs methods(described earlier in the disclosure) can be utilized, which saves areaand reduces FETs sizes carrying lower capacitances in the iDAC's currentreference network, which in turn lowers cost, reduces the size, andimproves the transient response of the D_(i)D_(o) sMACiDAC that utilizessuch iDACs.

Third, as noted earlier, operating in current mode has the followingbenefits for the disclosed D_(i)D_(o) sMACiDAC: (a) current mode isinherently fast, (b) voltage swings in current-mode signal processingare small, which enables operating with lower power supply voltage andoperating at low supply voltages facilitates reducing power consumption,(c) current-mode signal processing such as addition or subtractionfunctions take small area and can be performed fast.

Fourth, there are no passive devices in the disclosed D_(i)D_(o)sMACiDAC of FIG. 16, and as such it does not require resistors orcapacitors, which reduces manufacturing size and cost.

Fifth, the precision of the disclosed D_(i)D_(o) sMACiDAC can beimproved by improving the accuracy of iDACs (for example) by segmentingthe iDAC's reference current transfer-function (along with digitalbinary-to-thermometer logic decoding of iDAC's digital input code).

Sixth, the disclosed D_(i)D_(o) sMACiDAC of FIG. 16 can utilize lowerresolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplicationfunction, which occupy smaller areas, but can still deliver higheraccuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. Forexample, higher than 3 of 5 bits of accuracy for iDACs is attainable instandard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%)matching that is achievable between the iDAC's binary weighted currentsources or segmented current sources. As such, the disclosed D_(i)D_(o)sMACiDAC can utilize low resolution iDACs that occupy small areas butstill achieve higher accuracy multiply-accumulate performance at lowercost.

Seventh, dynamic power consumption is lower because the D_(i)D_(o)sMACiDAC by utilizing floating, factorized, or combination of floatingand factorized iDACs which have smaller sized FETs (in theinput-to-output transfer function network) which would consume lessdynamic current to drive smaller FET devices during digital input codetransitions.

Eight, the D_(i)D_(o) sMACiDAC that utilizes floating iDAC can bearranged free of clock, suitable for asynchronous (clock free)computation.

Ninth, the D_(i)D_(o) sMACiDAC that utilizes same type of MOSFET currentsources and MOSFET switches in the respective floating, factorized, orcombination of floating and factorized iDACs, which are symmetric,matched, and scaled. Such arrangement facilitates device parameters totrack each other over process, temperature, and operating conditionvariations. Accordingly, the D_(i)D_(o) sMACiDAC's temperaturecoefficient, power supply coefficient, and AC power supply rejectionperformance can be enhanced.

Tenth, while digital computation is generally accurate but it may beexcessively power hungry. Current-mode analog and mixed-signalcomputation that is disclosed here can be approximate but signalprocessing can be accomplished asynchronously and power consumption canbe lower. Moreover, analog current errors here generally may result indegradation but (not total failures) of analog computation, whichprovides the end-application with approximate results to work withinstead of experiencing failed results.

Thirteenth, utilizing plurality of iDACs, whose outputs are summed,would attenuate the statistical contribution of the cumulative iDAC'srandom errors (such as random noise, offset, mismatches, linearity,gain, drift, etc.) at the summing node where the iDAC's current outputsare coupled. The statistical contribution of such cumulative iDAC'srandom errors, at the summing node, is the square root of the sum of thesquares of such random error terms.

Section 17—Description of FIG. 17

FIG. 17 is a simplified functional block diagram illustrating anembodiment of a mixed-signal current-mode multiply-accumulate (iMACiDAC)circuit. The disclosed iMACiDAC is a mixed-signal current-modedigital-input to digital-output (D_(i)D_(o)) multiply-accumulate (iMAC)circuit plus bias circuit utilizing current-modedigital-to-analog-converters (iDAC) and current-mode analog-to-digitalconverters (iADC).

The D_(i)D_(o) iMACiDAC embodiment disclosed in FIG. 17 is arranged witha plurality of weight iDACs to generate a plurality of weight currentsignals that feed the reference input of a respective plurality of dataiDACs. A respective plurality of the data iDACs outputs generate arespective plurality of products as analog current representations of arespective plurality of the weight iDACs input signals multiplied by arespective plurality of the data iDACs input signals. The respectiveplurality of the data iDACs outputs are coupled together to generate asummation current signal that is then added to a bias current signal togenerate a final summation current signal, wherein the bias currentsignal is programmed by a bias iDAC. This final summation current signalis digitized via a current-mode analog-to-digital-converter (iADC) whosedigital outputs represent a summation of bias iDAC input signal addedwith a summation of the products of the respective weight iDAC inputsignals multiplied by the respective data iDAC input signals.

FIG. 17 discloses an embodiment that performs a multiply-accumulatefunction by performing analog and mixed-signal processing utilizingcurrent-mode data-converters, arranged in such a way to leverage thedistributive property of multiplication, which save area and improveperformance of multiply-accumulate functions needed in AI and MLapplications. As such, the embodiment disclosed in FIG. 17, performs thefunction of

${\sum\limits_{i = 1}^{p}\left( {{D_{i} \times W_{i}} + b} \right)},$where D_(i) is plurality of ‘data current signals’ with p as plurality(e.g., p=3 of D_(i) can be generated by iDACs₁₇, iDACt₁₇, and iDACu₁₇),W_(i) is plurality of ‘weight current signals’ with p again as plurality(e.g., again with p=3 of W_(i) current signals that can be generated byiDACw₁₆, iDACx₁₆, and iDACy₁₆, respectively), and b is ‘bias currentsignal’ (e.g., b current signal can be generated by DACb₁₇). Asindicated in prior sections, the illustration of FIG. 17 depicts(plurality) p=3 for clarity of description, but n can be a sea ofmultiplying iDAC channels depending on application and as many as 1000.

In FIG. 17, a weight iDACw_(i7) is supplied with a reference currentsignal I4 ₁₇ at its wR₁₇ port. Also, iDACw₁₇ receives a w-bits widedigital input word Dw₁₇, and accordingly iDACw₁₇ generates an analogoutput current signal Aw₁₇. Concurrently, a data iDACs₁₇ is suppliedwith Aw₁₇ at its sR₁₇ reference input port, while iDACs₁₇ receives as-bits wide digital input word Ds₁₇, and accordingly iDACs₁₇ generatesan analog output current signal As₁₇×Aw₁₇, which represents the productof w ‘weight current signal’ multiplied by s ‘data current signal’.

A weight iDACx₁₇ is supplied with a reference current signal I3 ₁₇ atits xR₁₇ port. Also, iDACx₁₇ receives a v-bits wide digital input wordDx₁₇, and accordingly iDACx₁₇ generates an analog output current signalAx₁₇. Concurrently, a data iDACt₁₇ is supplied with Ax₁₇ at its tR₁₇reference input port, while iDACt₁₇ receives a t-bits wide digital inputword Dt₁₇, and accordingly iDACt₁₇ generates an analog output currentsignal At₁₇×Ax₁₇, which represents the product of x ‘weight currentsignal’ multiplied by t ‘data current signal’.

A weight iDACy₁₇ is supplied with a reference current signal I2 ₁₇ atits yR₁₇ port. Also, iDACy₁₇ receives a y-bits wide digital input wordDy₁₇, and accordingly iDACy₁₇ generates an analog output current signalAy₁₇. Concurrently, a data iDACu₁₇ is supplied with Ay₁₇ at its uR₁₇reference input port, while iDACu₁₇ receives a u-bits wide digital inputword Du₁₇, and accordingly iDACu₁₇ generates an analog output currentsignal Au₁₇×Ay₁₇, which represents the product of y ‘weight currentsignal’ multiplied by u ‘data current signal’.

A bias iDACb₁₇ is supplied with a reference current signal I1 ₁₇ at itsbR₁₇ reference input port. Also, iDACb₁₇ receives a b-bits wide digitalinput word Db₁₇, and accordingly iDACb₁₇ generates an analog outputcurrent signal Ab₁₇.

The output of iDACb₁₇, iDACs₁₇, iDACt₁₇, and iDACu₁₇ are coupledtogether to generate a final summation current signal representing(Au₁₇×Ay₁₇+At₁₇×Ax₁₇+As₁₇×Aw₁₇)+Ab₁₇.

This final summation current signal is concurrently fed onto a currentinput port of iADC₁₇ which is a current-mode analog-to-digital-converter(iADC), which generates a o-bits wide digital output word Do₁₇ which isthe digital representation of the D_(i)D_(o) iMACiDAC output signal(Au₁₇×Ay₁₇+At₁₇×Ax₁₇+As₁₇×Aw₁₇)+Ab₁₇.

In summary, the embodiment of D_(i)D_(o) sMACiDAC circuit illustrated inFIG. 17 processes signals in current-mode utilizing iDACs has thefollowing benefits:

First, the disclosed D_(i)I_(o) sMACiDAC utilizing plurality ofcurrent-mode iDACs whose certain outputs can be coupled together andbiased in current mode, which saves area and lowers cost, and improvedperformance with faster dynamic response, in part for its efficacy inperforming summation in current-mode that can be accomplished by simplycoupling plurality of current signals.

Second, standard iDACs or factorized or floating iDACs methods(described earlier in the disclosure) can be utilized, which saves areaand reduces FETs sizes carrying lower capacitances in the iDAC's currentreference network, which in turn lowers cost, reduces the size, andimproves the transient response of the D_(i)D_(o) sMACiDAC that utilizessuch iDACs.

Third, as noted earlier, operating in current mode has the followingbenefits for the disclosed D_(i)D_(o) sMACiDAC: (a) current mode isinherently fast, (b) voltage swings in current-mode signal processingare small, which enables operating with lower power supply voltage andoperating at low supply voltages facilitates reducing power consumption,(c) current-mode signal processing such as addition or subtractionfunctions take small area and can be performed fast.

Fourth, there are no passive devices in the disclosed D_(i)D_(o)sMACiDAC of FIG. 17, and as such there is no need for resistors orcapacitors, which reduces manufacturing size and cost.

Fifth, the precision of the disclosed D_(i)D_(o) sMACiDAC can beimproved by improving the accuracy of iDACs (for example) by segmentingthe iDAC's reference current transfer-function (along with digitalbinary-to-thermometer logic decoding of iDAC's digital input code).

Sixth, the disclosed D_(i)D_(o) sMACiDAC of FIG. 17 can utilize lowerresolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplicationfunction, which occupy smaller areas, but can still deliver higheraccuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. Forexample, higher than 3 of 5 bits of accuracy for iDACs is attainable instandard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%)matching that is achievable between the iDAC's binary weighted currentsources or segmented current sources. As such, the disclosed D_(i)D_(o)sMACiDAC can utilize low resolution iDACs that occupy small areas butstill achieve higher accuracy multiply-accumulate performance at lowercost.

Seventh, dynamic power consumption is lower because the D_(i)D_(o)sMACiDAC by utilizing floating, factorized, or combination of floatingand factorized iDACs could have smaller sized FETs (in theinput-to-output transfer function network) which would consume lessdynamic current to drive smaller FET devices during digital input codetransitions.

Eight, the D_(i)D_(o) sMACiDAC that utilizes floating iDAC can bearranged free of clock, suitable for asynchronous (clock free)computation.

Ninth, the D_(i)D_(o) sMACiDAC that utilizes same type of MOSFET currentsources and MOSFET switches in the respective floating, factorized, orcombination of floating and factorized iDACs, which are symmetric,matched, and scaled. Such arrangement facilitates device parameters totrack each other over process-temperature-operation conditionsvariations. Accordingly, the D_(i)D_(o) sMACiDAC's temperaturecoefficient, power supply coefficient, and AC power supply rejectionperformance can be enhanced.

Tenth, while digital computation is generally accurate but it may beexcessively power hungry. Current-mode analog and mixed-signalcomputation that is disclosed here can be approximate but signalprocessing can be accomplished asynchronously and power consumption canbe lower. Moreover, analog current errors here generally may result indegradation but (not total failures) of analog computation, whichprovides the end-application with approximate results to work withinstead of experiencing failed results.

Eleventh, utilizing plurality of iDACs, whose outputs are summed, wouldattenuate the statistical contribution of the cumulative iDAC's randomerrors (such as random noise, offset, mismatches, linearity, gain,drift, etc.) at the summing node where the iDAC's current outputs arecoupled. The statistical contribution of such cumulative iDAC's randomerrors, at the summing node, is the square root of the sum of thesquares of such random error terms.

Section 18—Description of FIG. 18

FIG. 18 is a simplified functional block diagram illustrating anembodiment of a mixed-signal current-mode Artificial Neural Network(iANN) circuit. The disclosed iANN is a mixed-signal current-modedigital-input to digital-output (D_(i)D_(o)) iANN circuit utilizingcurrent-mode multiply-accumulate (iMAC) circuits that utilizecurrent-mode digital-to-analog-converter (iDAC) and current-modeanalog-to-digital converter (iADC) circuits.

Consider that in the FIG. 18 illustrates 3 channels of iDACs (e.g.,iDACm₁₈-iDACn₁₈-iDACo₁₈, or iDACp₁₈-iDACq₁₈-iDACr₁₈, oriDACs₁₈-iDACt₁₈-iDACu₁₈, or iDACx₁₈-iDACy₁₈-iDACz₁₈, oriDACa₁₈-iDACb₁₈-iDACc₁₈, and so on) for clarity of description andillustration purposes only, but 3 channels are not a limitation of thisdisclosure. For example, a sea of iDACs (e.g., less than 1000 channels)can be utilized here depending on end-applications.

In FIG. 18, an iDACx₁₈ receives a reference current signal xR₁₈, ax-bits wide digital input word Dx₁₈, and generates an analog outputcurrent signal Ax₁₈. Keep in mind that the Ax₁₈ can be replicated, asillustrated in FIG. 15, and supplied to plurality of reference inputs ofa respective plurality of iDACs comprising of iDACm₁₈, iDACn₁₈, andiDACo₁₈. Accordingly, an iDACm₁₈ receives a m-bits wide digital inputword Dm₁₈, and generates an analog output current signal Ax₁₈×Am₁₈. AniDACn₁₈ receives a n bits wide digital input word Dn₁₈, and generates ananalog output current signal Ax₁₈×An₁₈. An iDACo₁₈ receives a o-bitswide digital input word Do₁₈, and generates an analog output currentsignal Ax₁₈×Ao₁₈.

An iDACy₁₈ receives a reference current signal yR₁₈, a y-bits widedigital input word Dy₁₈, and generates an analog output current signalAy₁₈. Also, bear in mind that the Ay₁₈ can be replicated, similarly asillustrated in FIG. 15, and supplied to plurality of reference inputs ofa respective plurality of iDACs comprising of iDACp₁₈, iDACq₁₈, andiDACr₁₈. Accordingly, an iDACp₁₈ receives a p-bits wide digital inputword Dp₁₈, and generates an analog output current signal Ay₁₈×Ap₁₈. AniDACq₁₈ receives a q bits wide digital input word Dq₁₈, and generates ananalog output current signal Ay₁₈×Aq₁₈. An iDACr₁₈ receives a r-bitswide digital input word Dr₁₈, and generates an analog output currentsignal Ay₁₈×Ar₁₈.

An iDACz₁₈ receives a reference current signal zR₁₈, a z-bits widedigital input word Dz₁₈, and generates an analog output current signalAz₁₈. Also, notice that the Az₁₈ can be replicated, similarly asillustrated in FIG. 15, and supplied to plurality of reference inputs ofa respective plurality of iDACs comprising of iDACs₁₈, iDACt₁₈, andiDACu₁₈. Accordingly, an iDACs₁₈ receives a s-bits wide digital inputword Ds₁₈, and generates an analog output current signal Az₁₈×As₁₈. AniDACt₁₈ receives a t-bits wide digital input word Dt₁₈, and generates ananalog output current signal Az₁₈×At₁₈. An iDACu₁₈ receives a u-bitswide digital input word Du₁₈, and generates an analog output currentsignal Az₁₈×Au₁₈.

A bias iDACa₁₈ receives a reference current signal aR₁₈, a a-bits widedigital input word Da₁₈, and generates an analog output current signalAa₁₈. A bias iDACb₁₈ receives a reference current signal bR₁₈, a b-bitswide digital input word Db₁₈, and generates an analog output currentsignal Ab₁₈. A bias iDACc₁₈ receives a reference current signal cR₁₈, ac-bits wide digital input word Dc₁₈, and generates an analog outputcurrent signal Ac₁₈.

The outputs of iDACm₁₈, iDACp₁₈, and iDACs₁₈ are coupled together andcoupled with output of bias iDACa₁₈ which generates the summation analogcurrent signal that is a multiply-accumulate analog current signalIa_(iMAC)=[Aa₁₈+(Ax₁₈×Am₁₈+Ay₁₈×Ap₁₈+Az₁₈×As₁₈)] which can beindependently digitized through an iADC or can be fed onto an input of acurrent mux (iMux) as depicted by iMUX₁₈.

Also, the outputs of iDACn₁₈, iDACq₁₈, and iDACt₁₈ are coupled togetherand coupled with output of bias iDACb₁₈ which generates the summationanalog current signal that is another multiply-accumulate analog currentsignal M_(iMAC)=[Ab₁₈+(Ax₁₈×An₁₈+Ay₁₈×Aq₁₈+Az₁₈×At₁₈)] which can beindependently digitized through another input of a current mux (iMux) asdepicted by iMUX₁₈.

Moreover, the outputs of iDACn₁₈, iDACq₁₈, and iDACt₁₈ are coupledtogether and coupled with output of bias iDACb₁₈ which generates thesummation analog current signal that is another multiply-accumulateanalog current signal IC_(iMAC)=[Ab₁₈ (Ax₁₈×An₁₈+Ay₁₈×Aq₁₈+Az₁₈×At₁₈)]which can be independently digitized through an iADC or can be fed ontoanother input of a current mux (iMux) as depicted by iMUX₁₈.

A current mux (such as FIG. 18 illustration of an iMUX₁₈ which is a3-to-1 channel analog current mux) with plurality of inputs and oneoutput can consecutively select with (S₁₈) and steer themultiply-accumulate analog current signals Ia_(iMAC), Ib_(iMAC), andIc_(iMAC) into iADC₁₈ to digitize the said multiply-accumulate analogcurrent signals at its output D₁₈.

Notice that there is flexibility in programming the FIG. 18's iDACsreference signals (e.g., xR₁₈, yR₁₈, zR₁₈, aR₁₈, bR₁₈, cR₁₈, R₁₈) suchas programming xR₁₈=yR₁₈=zR₁₈. Also, depending on the end-applicationrequirements, to save area and current consumption, one bias iDAC can bearranged with its output replicated and supplied to plurality ofmultiply-accumulate analog current nodes, instead of utilizing pluralityof bias iDACs (e.g., iDACa₁₈, iDACb₁₈, and iDACc_(i8)). Moreover, thereference signal of the iADC₁₈ can be programmed to accommodate the zeroto full scale current signals of the plurality of multiply-accumulateanalog currents (e.g., Ia_(iMAC), Ib_(iMAC), and Ic_(iMAC)).

In summary, the current-mode Artificial Neural Network (iANN) circuit inillustrated FIG. 18 is a mixed-signal digital-input to digital-output(D_(i)D_(o)) iANN that is arranged with plurality of current-modemultiply-accumulate (iMAC) circuits, wherein the iMAC circuits utilizecurrent-mode digital-to-analog-converter (iDAC) and current-modeanalog-to-digital converter (iADC) circuits. As such, the disclosed iANNhas the following benefits:

First, in part, because summation is a key part of iANN that arearranged with iMAC circuits that utilize iDAC circuits, a simplecoupling of iDAC current outputs generates a summation signal in a smallarea, asynchronously, and at high speeds (since current mode signalprocessing is inherently fast.

Second, standard iDACs or factorized or floating iDACs methods(described earlier in the disclosure) can be utilized here, which savesarea and reduces FETs sizes carrying lower capacitances in the iDAC'scurrent reference network, which in turn lowers cost, reduces the size,and improves the transient response of the iANN.

Third, as noted earlier, operating the iANN in current-mode reducesvoltage swings, which enables operating with lower power supply voltageand operating at low supply voltages facilitates reducing powerconsumption. Additionally, the flexibility to run the CMOSFETs insubthreshold enables the iDACs (and hence the iANN) to operate withultra-low currents, even lower power supplies, and ultra-low powerconsumption suitable for mobile applications.

Fourth, there are no passive devices in the disclosed iANN, and as suchthere is no need for resistors or capacitors, which reducesmanufacturing size and cost.

Fifth, the precision of the disclosed iANN can be improved by improvingthe accuracy of iDACs (for example) by segmenting the iDAC's referencecurrent transfer-function (along with digital binary-to-thermometerlogic decoding of iDAC's digital input code).

Sixth, the iANN can utilize lower resolution iDACs (e.g., 3-bits or5-bits) to perform the multiplication function, which occupy smallerareas, but can still deliver higher accuracy (e.g., 8-bits of accuracyor ±0.4%) which is beneficial. For example, higher than 3 of 5 bits ofaccuracy for iDACs is attainable in standard CMOS fabrication factoriesdue to (8-bits of accuracy or ±0.4%) matching that is achievable betweenthe iDAC's binary weighted current sources or segmented current sources.As such, the disclosed iANN can utilize low resolution iDACs that occupysmall areas but still achieve higher accuracy multiply-accumulateperformance at lower cost.

Seventh, dynamic power consumption is lower because iANN can utilizefloating, factorized, or combination of floating and factorized iDACswhich have smaller sized FETs (in the input-to-output transfer functionnetwork) which would consume less dynamic current to drive smaller FETdevices during digital input code transitions.

Eight, the iANN that utilizes floating iDAC can be arranged free ofclock, suitable for asynchronous (clock free) computation.

Ninth, the iANN that utilizes same type of MOSFET current sources andMOSFET switches in the respective floating, factorized, or combinationof floating and factorized iDACs, which are symmetric, matched, andscaled. Such arrangement facilitates device parameters to track eachother over process-temperature-operation conditions variations.Accordingly, the iANN temperature coefficient, power supply coefficient,and AC power supply rejection performance can be enhanced.

Tenth, while digital computation is generally accurate but it may beexcessively power hungry. Methods of current-mode analog andmixed-signal computation that is disclosed here can be approximate butsignal processing can be accomplished asynchronously and powerconsumption can be lower. Moreover, analog current errors here generallymay result in degradation but (not total failures) of analogcomputation, which provides the end-application with approximate resultsto work with instead of experiencing failed results.

Eleventh, utilizing plurality of iDACs, whose outputs are summed, wouldattenuate the statistical contribution of the cumulative iDAC's randomerrors (such as random noise, offset, mismatches, linearity, gain,drift, etc.) at the summing node where the iDAC's current outputs arecoupled. The statistical contribution of such cumulative iDAC's randomerrors, at the summing node, is the square root of the sum of thesquares of such random error terms.

Section 19—Description of FIG. 19

FIG. 19 is a simplified circuit schematic diagram illustrating anembodiment of a multi-channel mixed-signal current-modedigital-to-analog converter (iDAC) utilizing the multiple-channeldata-converter method.

One of the objectives of this disclosure is to make multiple-channel(sea of) iDACs with medium-to-high (6-bits to 12-bits) resolution thatis small size and low cost. Low cost and small size of sea of iDACs havebroad applications, including in machine learning (ML) and artificialintelligence (AI) applications wherein 1000s of iDACs may be utilized aspart of for example the multiply-accumulate (MAC) function.

Another objective of this disclosure is to make multiple-channel (seaof) current mode analog to digital converters (iADCs). Similarly, lowcost and small size of sea of iADCs have broad base of applicationsincluding in ML & AI applications where a plurality of sums of theoutputs of a plurality of current-mode MACs (iMACs) may need to beconverted to digital signals. The first segments of this sectiondescribe iDACs.

For clarity of description, FIG. 19 illustrates only 4-channels of 6-bitiDACs, and this illustration is not a limitation of the disclosure here.Depending on application requirements, the disclosed multiple-channeldata-converter method could have 1000s of channels where each iDAC can,for example, have 16-bits of resolution.

Note that for example, in a conventional 6-bit binary iDACs with an LSBcurrent weight of i, binary current source network comprising of currentsources (2⁶⁻¹)i, (2⁵⁻¹)i, (2⁴⁻¹)i, (2³⁻¹)i (2²⁻¹)i, and (2¹⁻¹)i aregenerated by arranging plurality of paralleled current reference cells.Generally, each current cell is a non-minimum W/L=X carrying an LSBcurrent weight (e.g., i). In a conventional iDAC, identical cells havinga 1X (W/L size carrying an LSB current weight of i) are, for example,replicated in parallel 32X, 16X, 8X, 4X, 2X, and 1X times to generatethe respective binary reference currents of 32i, 16i, 8i, 4i_(r) 2i, and1i. Utilizing identical current cells (which dominate the accuracy of aniDACs and that are arranged in parallel to generate the respectivebinary reference currents) improves the matching between respectivebinary weighted reference currents, and optimizes the iDAC's accuracy.

As an example, in a conventional 6-bit iDAC the binary weighted currentswould require 127 LSB current cells. A conventional 8-bit iDAC's binaryweighted currents would require 255 LSB current cells. Thus, a16-channel conventional 6-bit iDAC array would require about 127×16=2032LSB current cells and an 8-bit iDAC array would require about255×16=4080 LSB current cells. In order to attain medium to highaccuracy targets for the iDACs, the LSB current cells need to bepatterned with non-minimum (larger) size W and L, and as such thenumerous LSB current cells which are combined in parallel, dominate thearea of the iDACs. As such, conventional iDACs with medium to largeresolution are generally prohibitively large and impractical for AI andML applications that require (numerous channels) sea of iDACs.

Operating in current mode, an iDAC is generally fast. However, becauseof the numerous paralleled LSB current cells required in conventionalmedium to high resolution iDACs, the combined parasitic and straycapacitance associated with the array of paralleled LSB current cellswould slow down the circuit. For example, in an 8-bit iDAC, the 8th bitor the MSB is comprised of 128× parallel LSB current cells and 7^(th)bit is comprised of 64× parallel LSB current cells and so on. Besidesoccupying large die area, the large size of paralleled current cells canslow down the dynamic response of the conventional iDACs, cause glitchinto the iDAC's analog output as well as the power supplier, andincrease dynamic current consumption. Consequently, the overall dynamicperformance of the iDACs and AI and ML end-system could be degraded.

The disclosed invention, utilizing a multiple-channel data-convertermethod, substantially reduces the number of the current cells (andthereby minimizes the area of the disclosed iDACs) which makes feasibleutilizing sea of the disclosed iDACs with a low cost. Moreover,plurality of the disclosed iDACs with substantially fewer current cells,lowers the combined associated parasitic and stray capacitanceassociated with current reference cells, which improves the disclosediDAC's dynamic response, lowers glitch, lowers digital injections intopower supplies, and reduces the disclosed iDAC's dynamic powerconsumption.

A multiple-channel data-converter method disclosed here arranges aplurality of n-bit iDACs, wherein each of the iDACs is comprised of avoltage controlled current sources (VCCS) to generate each iDAC's binaryweighted currents. With i representing an LSB current weight, themultiple-channel data-converter method utilizes a reference bias network(RBN₁₉) that generates a sequence of individual binary weightedreference bias currents from (2^(n−1))i to (2¹⁻¹)i that are inputted toa sequence of current controlled voltage sources (CCVS). In turn, thesequences of CCVSs generate a sequence of reference bias voltage busesthat correspond to the sequence of binary weighted reference biascurrents (2^(n−1))i to (2¹⁻¹)i. The respective output ports of CCVSs,which are a sequence of reference bias voltage busses are coupled to theinput of the sequence of the respective plurality of iDACs' VCCSs, thatcorrespond to the respective binary weighted reference bias currentsfrom (2^(n−1))i to (2¹⁻¹)i.

By utilizing the multiple-channel data-converter method, the referencecurrent network of an iADC or that of a plurality of iADCs can also besupplied with sequence of reference bias voltage buses that can bias thesequence of binary weighted reference bias currents (2^(n−1))i to(2¹⁻¹)i of the iADC or the plurality of iADCs. As such, themultiple-channel data-converter method enables decoupling the weight ofa current source from the scaling of the size current source nodecapacitances of the iADC's current reference networks. This trait,beside saving on die area, can substantially reduce node capacitancealong the iADC's signal paths which can speed up the iADC (e.g., thelarger the W/L size of a FET current source the larger its capacitanceand the slower the node).

Consider that the multiple-channel data-converter method can also bearranged such that a RBN would generate a sequence of individualreference bias currents that are non-linear (e.g., square orlogarithmic) where the sequence of individual reference bias currentscan then bias the current reference networks (transfer function) formultiple-channels of non-linear iDACs, wherein as a result each of thenon-liner iDAC's current reference network would follow a non-linear(e.g., square or logarithmic) digital input to analog current outputtransfer function.

For example, if a RBN is programmed to approximate a logarithmictransfer function, then a pair of iDACs (e.g., iDAC_(log X) andiDAC_(log Y)) whose reference current networks are biased from thelogarithmic RBN can each generate logarithmic outputs in response totheir digital inputs (e.g., D_(X), and D_(Y)). Coupling the outputs ofthe pair of logarithmic iDAC_(X) and iDAC_(Y) would generate a currentoutput that is an analog representation of the product of D_(log X) andD_(log Y) in the logarithmic domain (i.e., analog current representationof log[D_(X)×D_(Y)]. This can be a cost-performance effectivearrangement to perform, for example, 1000s of multiplications on one ICby utilizing plurality of pairs of logarithmic iDACs (whose digitalinput to analog output transfer functions are programmedlogarithmically), wherein each logarithmic iDAC can have small referencecurrent network that is biased from the same logarithmic RBN.

An alternative example could be to program a RBN that follows anapproximate square function. As such a pair of square iDACs (e.g.,iDAC_((x+y)) ₂ and iDAC_((x−y)) ₂ ) whose reference current networks arebiased from the square RBN. Accordingly, each pair of iDAC_((x+y)) ₂ andiDAC_((x−y)) ₂ can generate square outputs in response to the summationand subtraction of their respective digital inputs (e.g., D_(X)+D_(Y),and D_(Y)−D_(Y)). Bear in mind that multiplication can be performed by aquarter square operation, wherein (X+Y)²−(X−Y)²=4×X×Y. Therefore, bysubtracting the outputs of the pair of iDAC_((x+y)) ₂ and iDAC_((x−y)) ₂, we can generate a current output that is an analog representation ofthe product of D_(X) and D_(Y) times a scale factor (e.g., scalefactor=4). The subtraction operation in current mode can be accomplishedcost-performance effectively by feeding the iDAC_((x+y)) ₂ andiDAC_((x−y)) ₂ current outputs to the input port and output port of acurrent mirror, respectively. This also can be a cost-performanceeffective arrangement to perform, for example, 1000s of multiplicationsin one IC by utilizing plurality of pairs of square iDACs (wherein eachof the iDAC's digital input to analog output transfer functions areprogrammed squarely), wherein each square iDAC has a small referencecurrent network that is biased from the same square RBN. FIG. 42illustrates atypical simulations of a square iDAC's input-outputwaveform and linearity, which will be described later.

As noted earlier, for clarity of description, FIG. 19 illustrates anembodiment of the multiple-channel data-converter method with a4-channels of iDACs wherein each iDAC has 6-bits of resolution. Here,the four channels of iDACs are iDACa₁₉, iDACb₁₉, iDACc₁₉, and iDACd₁₉,whose current source networks are biased via reference bias network(RBN₁₉) circuit.

In FIG. 19, a RBN₁₉ generates a sequence of individual binary weightedreference bias currents as follows: P32 r ₁₉ operating at I_(D) of(2⁶⁻¹)×i=32i; P16 r ₁₉ operating at I_(D) of (2⁵⁻¹)×i=16i; P8 r ₁₉operating at I_(D) of (2⁴⁻¹)×i=8i; P4 r ₁₉ operating at I_(D) of(2³⁻¹)×i=4i; P2 r ₁₉ operating at I_(D) of (2²⁻¹)×i=2i; and P1 r ₁₉operating at I_(D) of (2¹⁻¹)×i=1i. In the embodiment of FIG. 19, RBN₁₉is comprised of a sequence of CCVS which are implemented as a sequenceof diode connected NMOSFETs (N32 r ₁₉, N16 r ₁₉, N8 r ₁₉, N4 r ₁₉, N2 r₁₉, and N1 r ₁₉) whose gate and drain ports are coupled together,wherein each NMOSFET is scaled with a W/L=1X. Accordingly, the sequenceof binary weighted reference bias currents I32 r ₁₉ to I1 r ₁₉ areinputted to the diode connected NMOSFETs (CCVS) which generate asequence of (gate-to-source) reference bias voltages from reference biasvoltage bus V32 r ₁₉ to reference bias voltage bus V1 r ₁₉ as follows:I_(D) of P32 r ₁₉=32i is inputted to the (drain-gate ports of the) diodeconnected N32 r ₁₉ to generate a reference bias bus voltage of V32 r ₁₉;I_(D) of P16 r ₁₉=16i is inputted to the diode connected N16 r ₁₉ togenerate a reference bias bus voltage of V16 r ₁₉; I_(D) of P8 r ₁₉=8iis inputted to the diode connected N8 r ₁₉ to generate a reference biasbus voltage of V8 r ₁₉; I_(D) of P4 r ₁₉=4i is inputted to the diodeconnected N4 r ₁₉ to generate a reference bias bus voltage of V4 r ₁₉;I_(D) of P2 r ₁₉=2i is inputted to the diode connected N2 r ₁₉ togenerate a reference bias bus voltage of V2 r ₁₉; and I_(D) of P1 r₁₉=1i is inputted to the diode connected N1 r ₁₉ to generate a referencebias bus voltage of V1 r ₁₉.

The iDACa₁₉ receives a digital input word Da₁₉ that is a=6 bits wide andgenerates a positive and a negative output currents I_(a) ₁₉ ⁺ and I_(a)₁₉ ⁻, respectively. Here, N32 a ₁₉ which is scaled with W/L=1X (andfunctioning as iDACa₁₉'s 6^(th) bit's VCCC) receives the reference biasbus voltage V32 r ₁₉ at its gate port. As such, I_(D) of N32 a ₁₉mirrors that of the N32 r ₁₉, and generates I_(D)=32i for iDACa₁₉ whichis steered onto either I_(a) ₁₉ ⁺ or I_(a) ₁₉ ⁻ in accordance with (theMSB or) the 6^(th) bit's polarity of the Da₁₉ word. The N16 a ₁₉ whichis also scaled with W/L=1X (and functioning as iDACa₁₉'s 5^(th) bit'sVCCC) receives the reference bias bus voltage V16 r ₁₉ at its gate port.As such, I_(D) of N16 a ₁₉ mirrors that of the N16 r ₁₉, and generatesI_(D)=16i for iDACa₁₉ which is steered onto either I_(a) ₁₉ ⁺ or I_(a)₁₉ ⁻, in accordance with the 5^(th) bit's polarity of the Da₁₉ word. TheN8 a ₁₉ is also scaled with W/L=1X (and functioning as iDACa₁₉'s 4^(th)bit's VCCC) receives the reference bias bus voltage V8 r ₁₉ at its gateport. As such, I_(D) of N8 a ₁₉ mirrors that of the N8 r ₁₉, andgenerates I_(D)=8i for iDACa₁₉ which is steered onto either I_(a) ₁₉ ⁺or I_(a) ₁₉ ⁻, in accordance with the 4^(th) bit's polarity of the Da₁₉word. The N4 a ₁₉ which is also scaled with W/L=1X (and functioning asiDACa₁₉'s 3^(rd) bit's VCCC) receives the reference bias bus voltage V4r ₁₉ at its gate port. As such, I_(D) of N4 a ₁₉ mirrors that of the N4r ₁₉, and generates I_(D)=4i for iDACa₁₉ which is steered onto eitherI_(a) ₁₉ ⁺ or I_(a) ₁₉ ⁻ in accordance with the 3^(rd) bit's polarity ofthe Da₁₉ word. The N2 a ₁₉ which is also scaled with W/L=1X (andfunctioning as iDACa₁₉'s 2^(nd) bit's VCCC) receives the reference biasbus voltage V2 r ₁₉ at its gate port. As such, I_(D) of N2 a ₁₉ mirrorsthat of the N2 r ₁₉, and generates I_(D)=2i for iDACa₁₉ which is steeredonto either I4 ₉ or/Z, in accordance with the 2^(nd) bit's polarity ofthe Da₁₉ word. The N1 a ₁₉ which is also scaled with W/L=1X (andfunctioning as iDACa₁₉'s bit's VCCC) receives the reference bias busvoltage V1 r ₁₉ at its gate port. As such, I_(D) of N1 a ₁₉ mirrors thatof the N1 r ₁₉, and generates I_(D)=1i for iDACa₁₉ which is steered ontoeither I_(a) ₁₉ ⁺ or I_(a) ₁₉ ⁻ in accordance with the 1^(st) bit'spolarity of the Da₁₉ word.

The iDACb₁₉ receives a digital input word Db₁₉ that is b=6 bits wide andgenerates a positive and a negative output currents I_(b) ₁₉ ⁺ and I_(b)₁₉ ⁻, respectively. Here, N32 b ₁₉ which is scaled with W/L=1X (andfunctioning as iDACb₁₉'s 6^(th) bit's VCCC) receives the reference biasbus voltage V32 r ₁₉ at its gate port. As such, I_(D) of N32 b ₁₉mirrors that of the N3271 ₉, and generates I_(D)=32i for iDACb₁₉ whichis steered onto either I_(b) ₁₉ ⁺ or I_(b) ₁₉ ⁻ in accordance with (theMSB or) the 6^(th) bit's polarity of the Db₁₉ word. The N16 b ₁₉ whichis also scaled with W/L=1X (and functioning as iDACb₁₉'s 5^(th) bit'sVCCC) receives the reference bias bus voltage V16 r ₁₉ at its gate port.As such, I_(D) of N16 b ₁₉ mirrors that of the N16 r ₁₉, and generatesI_(D)=16i for iDACb₁₉ which is steered onto either I_(b) ₁₉ ⁺ or I_(b)₁₉ ⁻ in accordance with the 5^(th) bit's polarity of the Db₁₉ word. TheN8 b ₁₉ which is also scaled with W/L=1X (and functioning as iDACb₁₉'s4^(th) bit's VCCC) receives the reference bias bus voltage V8 r ₁₉ atits gate port. As such, I_(D) of N8 b ₁₉ mirrors that of the N8 r ₁₉,and generates I_(D)=8i for iDACb₁₉ which is steered onto either I_(b) ₁₉⁺ or I_(b) ₁₉ ⁻ in accordance with the 4^(th) bit's polarity of the Db₁₉word. The N4 b ₁₉ which is also scaled with W/L=1X (and functioning asiDACb₁₉'s 3^(rd) bit's VCCC) receives the reference bias bus voltage V4r ₁₉ at its gate port. As such, I_(D) of N4 b ₁₉ mirrors that of the N4r ₁₉, and generates I_(D)=4i for iDACb₁₉ which is steered onto eitherI_(b) ₁₉ ⁺ or I_(b) ₁₉ ⁻ in accordance with the 3^(rd) bit's polarity ofthe Db₁₉ word. The N2 b ₁₉ which is also scaled with W/L=1X (andfunctioning as iDACb₁₉'s 2^(nd) bit's VCCC) receives the reference biasbus voltage V2 r ₁₉ at its gate port. As such, I_(D) of N2 b ₁₉ mirrorsthat of the N2 r ₁₉, and generates I_(D)=2i for iDACb₁₉ which is steeredonto either I_(b) ₁₉ ⁺ or I_(b) ₁₉ ⁻ in accordance with the 2^(nd) bit'spolarity of the Db₁₉ word. The N1 b ₁₉ which is also scaled with W/L=1X(and functioning as iDACb₁₉'s 1^(st) bit's VCCC) receives the referencebias bus voltage V1 r ₁₉ at its gate port. As such, I_(D) of N1 b ₁₉mirrors that of the N1 r ₁₉, and generates I_(D)=1i for iDACb₁₉ which issteered onto either I_(b) ₁₉ ⁺ or I_(b) ₁₉ ⁻ in accordance with the1^(st) bit's polarity of the Db₁₉ word.

The iDACc₁₉ receives a digital input word Dc₁₉ that is c=6 bits wide andgenerates a positive and a negative output currents I_(c) ₁₉ ⁺ and I_(c)₁₉ ⁻, respectively. Here, N32 c ₁₉ which is scaled with W/L=1X (andfunctioning as iDACc₁₉'s 6^(th) bit's VCCC) receives the reference biasbus voltage V32 r ₁₉ at its gate port. As such, I_(D) of N32 c ₁₉mirrors that of the N32 r ₁₉, and generates I_(D)=32i for iDACc₁₉ whichis steered onto either I_(c) ₁₉ ⁺ or I_(c) ₁₉ ⁻, in accordance with (theMSB or) the 6^(th) bit's polarity of the Dc₁₉ word. The N16 c ₁₉ whichis also scaled with W/L=1X (and functioning as iDACc₁₉'s 5^(th) bit'sVCCC) receives the reference bias bus voltage V16 r ₁₉ at its gate port.As such, I_(D) of N16 c ₁₉ mirrors that of the N16 r ₁₉, and generatesI_(D)=16i for iDACc₁₉ which is steered onto either I_(c) ₁₉ ⁺ or I_(c)₁₉ ⁻, in accordance with the 5^(th) bit's polarity of the Dc₁₉ word. TheN8 c ₁₉ which is also scaled with W/L=1X (and functioning as iDACc₁₉'s4^(th) bit's VCCC) receives the reference bias bus voltage V8 r ₁₉ atits gate port. As such, I_(D) of N8 c ₁₉ mirrors that of the N8 r ₁₉,and generates I_(D)=8i for iDACc₁₉ which is steered onto either I_(c) ₁₉⁺ or I_(c) ₁₉ ⁻ in accordance with the 4^(th) bit's polarity of the Dc₁₉word. The N4 c ₁₉ which is also scaled with W/L=1X (and functioning asiDACc₁₉'s 3^(rd) bit's VCCC) receives the reference bias bus voltage V4r ₁₉ at its gate port. As such, I_(D) of N4 c ₁₉ mirrors that of the N4r ₁₉, and generates I_(D)=4i for iDACc₁₉ which is steered onto eitherI_(c) ₁₉ ⁺ or I_(c) ₁₉ ⁻ in accordance with the 3^(rd) bit's polarity ofthe Dc₁₉ word. The N2 c ₁₉ which is also scaled with W/L=1X (andfunctioning as iDACc₁₉'s 2^(nd) bit's VCCC) receives the reference biasbus voltage V2 r ₁₉ at its gate port. As such, I_(D) of N2 c ₁₉ mirrorsthat of the N2 r ₁₉, and generates I_(D)=2i for iDACc₁₉ which is steeredonto either I_(c) ₁₉ ⁺ or I_(c) ₁₉ ⁻ in accordance with the 2^(nd) bit'spolarity of the Dc₁₉ word. The N1 c ₁₉ which is also scaled with W/L=1X(and functioning as iDACc₁₉'s 1st bit's VCCC) receives the referencebias bus voltage V1 r ₁₉ at its gate port. As such, I_(D) of N1 c ₁₉mirrors that of the N1 r ₁₉, and generates I_(D)=1i for iDACc₁₉ which issteered onto either I_(c) ₁₉ ⁺ or I_(c) ₁₉ ⁻ in accordance with the1^(st) bit's polarity of the Dc₁₉ word.

Finally, iDACd₁₉ receives a digital input word Dd₁₉ that is d=6 bitswide and generates a positive and a negative output currents I_(d) ₁₉ ⁺and I_(d) ₁₉ ⁻, respectively. Here, N32 d ₁₉ which is scaled with W/L=1X(and functioning as iDACd₁₉'s 6^(th) bit's VCCC) receives the referencebias bus voltage V32 r ₁₉ at its gate port. As such, I_(D) of N32 d ₁₉mirrors that of the N32 r ₁₉, and generates I_(D)=32i for iDACd₁₉ whichis steered onto either I_(d) ₁₉ ⁺ or I_(d) ₁₉ ⁻ in accordance with (theMSB or) the 6^(th) bit's polarity of the Dd₁₉ word. The N16 d ₁₉ whichis also scaled with W/L=1X (and functioning as iDACd₁₉'s 5^(th) bit'sVCCC) receives the reference bias bus voltage V16 r ₁₉ at its gate port.As such, I_(D) of N16 d ₁₉ mirrors that of the N16 r ₁₉, and generatesI_(D)=16i for iDACd₁₉ which is steered onto either I_(d) ₁₉ ⁺ or I_(d)₁₉ ⁻ in accordance with the 5^(th) bit's polarity of the Dd₁₉ word. TheN8 d ₁₉ which is also scaled with W/L=1X (and functioning as iDACd_(n)'s4^(th) bit's VCCC) receives the reference bias bus voltage V8 r ₁₉ atits gate port. As such, I_(D) of N8 d ₁₉ mirrors that of the N8 r ₁₉,and generates I_(D)=8i for iDACd₁₉ which is steered onto either I_(d) ₁₉⁺ or I_(d) ₁₉ ⁻ in accordance with the 4^(th) bit's polarity of the Dd₁₉word. The N4 d ₁₉ which is also scaled with W/L=1X (and functioning asiDACd₁₉'s 3^(rd) bit's VCCC) receives the reference bias bus voltage V4r ₁₉ at its gate port. As such, I_(D) of N4 d ₁₉ mirrors that of the N4r ₁₉, and generates I_(D)=4i for iDACd₁₉ which is steered onto eitherI_(d) ₁₉ ⁺ or I_(d) ₁₉ ⁻ in accordance with the 3^(rd) bit's polarity ofthe Dd₁₉ word. The N2 d ₁₉ which is also scaled with W/L=1X (andfunctioning as iDACd₁₉'s 2^(nd) bit's VCCC) receives the reference biasbus voltage V2 r ₁₉ at its gate port. As such, I_(D) of N2 d ₁₉ mirrorsthat of the N271 ₉, and generates I_(D)=2i for iDACd₁₉ which is steeredonto either I_(d) ₁₉ ⁺ or I_(d) ₁₉ ⁻ in accordance with the 2^(nd) bit'spolarity of the Dd₁₉ word. The N1 d ₁₉ which is also scaled with W/L=1X(and functioning as iDACd₁₉'s bit's VCCC) receives the reference biasbus voltage V1 r ₁₉ at its gate port. As such, I_(D) of N1 d ₁₉ mirrorsthat of the N1 r ₁₉, and generates I_(D)=1i for iDACd₁₉ which is steeredonto either I_(d) ₁₉ ⁺ or I_(d) ₁₉ ⁻ in accordance with the 1^(st) bit'spolarity of the Dd₁₉ word.

In the embodiment of FIG. 19, the multiple-channel data-converter methodgenerates the binary weighted reference currents for plurality of iDACs(iDACa₁₉, iDACb₁₉, iDACc₁₉, and iDACd₁₉) via their respective sequenceof current source MOSFETs N32 ₁₉, N16 ₁₉, N8 ₁₉, N4 ₁₉, N2 ₁₉, and N1₁₉. These MOSFET are only scaled with W/L=1X, which results insignificant area savings. For a plurality of 6-bit iDACs (setting asideRBN₁₉'s area), every incremental iDAC utilizing the multiple-channeldata-converter method requires 6 of 1x size current sources, which isless than 10 times the area as compared to 64 of 1x size current sourcesrequired for a conventional 6-bit iDAC which requires a binary scalingof the MOSFET based current source network. Moreover, for a plurality of8-bit iDACs (setting aside RBN₁₉'s area), every incremental 8-bit iDACutilizing the multiple-channel data-converter method requires 8 of 1Xsize current sources, which is less than 25 times the area as comparedto 256 of 1X size current sources required for a conventional 8-bit iDACwhich requires binary scaled MOSFETs for its current source network.

Moreover, dynamic response of the iDACs is improved here because thedisclosed multiple-channel data-converter method substantially reducesthe number of MOSFETs that form the iDAC's binary weighted currentsource network. Fewer MOSFETs result in substantially less capacitancealong the iDAC's signal paths, which in turn improves the dynamicresponse of the iDACs, including reducing glitch and lowering dynamicpower consumption.

As indicated earlier, the MOSFETs that form a conventional iDAC's binaryweighted current sources need to be sized with meaningfully larger W andL than minimum geometry for better matching and thereby attaining higheraccuracy iDACs. Given their larger W/L sizes, a conventional iDAC'sbinary weighted current source network, dominate the area of such iDAC.Utilizing the multiple-channel data-converter method, accuracy isroughly comparable with that of a conventional iDAC by keeping thelarger (non-minimum MOSFETs) W/L size of the iDAC's current source.However, multiple-channel data-converter method reduces the number ofnon-minimum MOSFET utilizes in the iDAC's current sources, providingmeaningful die size reduction and cost savings.

Bear in mind that the multiple-channel data-converter method can beutilized for a portion of an iDAC's current source network (e.g., MSBbank) and conventional binary weighted iDAC can be utilized for theremainder portion (e.g., LSB bank) of iDAC's current source network.Also consider that the iDAC's current sources can utilize cascodedMOSFETs to attain higher output impedance, and the cascoded MOSFETs canbe biased with an independent bias bus, that feeds plurality of iDACs,similar in arrangement to those generated by RBN₁₉ circuit. Also, noticethat for example in applications requiring 8 or 16 or 32 channels iDACs,the area savings by utilize g the multiple-channel data-converter methodsignificantly outweighs the additional area due to RBN₁₉.

In summary, the current-mode multiple-channel data-converter method thatis illustrated in the embodiment of FIG. 19 discloses integratingmultiple mid-to-high resolution current-mode data-converters includingiDACs with the following benefits:

First, substantial area savings is achieved by utilizing the disclosedmultiple-channel data-converter method, especially in applicationsrequiring sea of iDACa in a chip. The area savings is achieved in partbecause the requirement for individually weighted current sources (e.g.,binary weighted or non-linearly weighted) is decoupled from requiringindividually scaled current sources.

Second, the disclosed multiple-channel data-converter methodsubstantially reduces the number of MOSFETs that form the iDAC's binaryweighted current source network. Fewer MOSFETs result in substantiallyless capacitance along the iDAC's signal paths, which in turn improvesthe dynamic response of the iDACs, including reducing glitch andlowering dynamic power consumption.

Third, despite area savings attainable by the disclosed multiple-channeldata-converter method, the accuracy of individual iDACs is notsubstantially deterred. All else substantially equal, the matching ofMOSFETs that form a data-converter's reference current network dominatethe accuracy of a current-mode data-converter. The scaled MOSFETs inboth the (central) reference bias network (RBN) match the 1X scaledMOSFETs in each of the iDAC because they are all arranged with the same(non-minimum W/L size) cell layout and same orientation.

Fourth, as noted earlier, operating the disclosed multiple-channeldata-converter method in current-mode is inherently fast. Moreover,operating in current mode reduces voltage swings along the pertinentsignal paths, which enables operating the iDACs with lower power supplyvoltages. Operating the data-converters at low power supply voltagesfacilitates reducing power consumption.

Fifth, the flexibility to run the MOSFETs in subthreshold enables theiDACs to operate with ultra-low currents, even lower power supplies, andultra-low power consumption suitable for mobile applications.

Sixth, there are no passive devices in the disclosed iDACs, and as suchthere is no need for resistors or capacitors, which reducesmanufacturing size and cost.

Seventh, the disclosed multiple-channel data-converter method can bearranged free of clock, suitable for asynchronous (clock free)computation.

Eighth, the disclosed multiple-channel data-converter method utilizesame type of MOSFET current sources and MOSFET switches which aresymmetric and matched. Such arrangement facilitates device parameters totrack each other over process-temperature-operation conditionsvariations. Accordingly, each of the data-coefficient, power supplycoefficient, and AC power supply rejection performance can be enhancedand matched between the plurality of data-converters.

Ninth and as stated earlier, the disclosed multiple-channeldata-converter method substantially reduces the number of MOSFETs thatfor example form the iDAC's binary weighted current source network, andas such the fewer MOSFETs can be placed closer to each other on a chip.Similarly, oriented and physically closer MOSFETs, that form the currentreference of a data-converter, generally match better which in turnimproves the accuracy of each of the data-converter and the matchingbetween them in plurality of iDACs in one chip.

Tenth, besides iDACs, the multiple-channel data-converter method can beapplied to iADCs as well. Generally and all else substantially equal,the larger the W/L size of a FET current source, the larger itscapacitance and the slower the node, which capacitively loads an iADC'scurrent reference networks and can substantially reduce the speed of theiADC. As noted earlier, the multiple-channel data-converter methodenables decoupling the weight of a current source from the scaling ofthe sizes of FETs utilizing in forming the data-converter's referencecurrent sources. By keeping each of the W/L sizes of the current sourceFETs the same at 1X and small for example (despite each of their binaryweighted currents), the node capacitances of the iADC's referencecurrent networks can be kept small which helps speeds up the dynamicresponse of the iADC. More importantly, in applications where plurality(sea of) iADCs are required, by keeping the size of the currentreference network of each of the iADC small in the plurality of theiADCs, substantial die area savings can also be realized.

Eleventh, in an embodiment of the multiple-channel data-converter methodwherein the central RBN is trimmed or calibrated for accuracy, theaccuracy of each of the plurality of data-converters whose referencecurrent network is biased from the same central RBN can be improved.

Twelfth, in an embodiment of the multiple-channel data-converter methodwherein the central RBN is desensitized from power supply variations(e.g., by utilizing the second power supply desensitization method orthe second PSR method disclosed in FIG. 40 and FIG. 41), the powersupply insensitivity of each of the plurality of data-converters whosereference current network is biased from the same central RBN can beimproved.

Thirteenth, the benefits of the multiple-channel data-converter methodcan be attained in other higher-order systems including but not limitedto multipliers, multiply-accumulate (MAC), and artificial-neural-network(ANN) that utilize the multiple-channel data-converter method.

Section 20—Description of FIG. 20

FIG. 20 is a simplified circuit schematic illustrating an embodiment fora plurality-channels of mixed-mode digital-input toanalog-current-output multiplier (XD_(i)I_(o)) that is multi-quadrant,wherein the XD_(i)I_(o) utilizes the multiple-channel data-convertermethod. The XD_(i)I_(o) of FIG. 20 (XD_(i)I_(o) ₂₀ ) utilizes anembodiment of the multiple-channel data-converter method disclosed insection 19 of this disclosure, which can save silicon area and improveiDAC's dynamic performance. The XD_(i)I_(o20) also utilizes a multiplierpower supply desensitization method (or XPSR method) that substantiallydesensitize XD_(i)I_(o)'s output current from power supply variations,while eliminating cascodes from current sources (which saves area).

For descriptive clarity and illustrative simplicity, the embodiment ofthe XD_(i)Io₂₀ that is depicted in FIG. 20 is a single channelmultiplier with 4-bits (x-word digital input) by 4-bits (y-word digitalinput) of resolution wherein the x and y digital words aresign-magnitude formatted, but the digital input resolutions can behigher (e.g., 6-bits to 12-bits) and the digital inputs can be arrangedwith other formats (e.g., binary, 2's complement, binary-offset, etc.)and plurality of channels can be in the 1000s.

As presented earlier, XD_(i)I_(o) ₂₀ embodiment utilizes themultiple-channel data-converter method wherein a reference bias network(RBN₂₀) generates a sequence of reference bias currents that aremirrored onto a plurality of iDAC's current reference networks, which isdescribed in section 19. The same RBN₂₀ can be utilized to mirror areference current (Ir₂₀) whose value is programmed at the full-scale ofIx₂₀ and Iy₂₀.

The XD_(i)Io₂₀ is comprising of a first current-output DAC (iDAC) oriDACx₂₀ that generates an output Ix₂₀, a second current-output iDAC oriDACy₂₀ that generates an out Iy₂₀, wherein Ix₂₀, Iy₂₀, and a referencecurrent (Ir₂₀) are inputted to a current multiplier or iMULT₂₀. Theresultant analog output product of iMULT₂₀ is Io₂₀ which is asingle-quadrant current output. The Io₂₀ is then inputted to a switchingcurrent mirror inverter (comprising of P1 s ₂₀, P2 s ₂₀, NoM₂₀, andNoM′₂₀) section of the iMULT₂₀ which converts the single-quadrant Io₂₀to a multi-quadrant output ±Io₂₀, wherein the plus minus sign of Io₂₀ iscontrolled by the sign bits of the x and y digital input words (e.g.,sign-magnitude format).

As noted earlier, the XD_(i)I_(o)'s dynamic performance is improved andsilicon area is reduced by utilizing the multiple-channel data-convertermethod that is described in section 19 of this disclosure. A single biasreference network (RBN₂₀) is shared by biasing a plurality XD_(i)I_(o)channels, wherein each XD_(i)I_(o) is comprising of iMULT (e.g., aniMULT₂₀) and pair of iDACs (e.g., iDACx₂₀ and iDACy₂₀). Here,substantially equal 1x sized current sources in the iDAC's referencecurrent network is biased separately by RBN₂₀ wherein each iDAC's 1Xsized current source carries its respective binary weighted current,which improves dynamic performance of the iDACs and save silicon area,especially in machine learning applications were 1000s (plurality) ofiDACs can be needed to perform the multiply-accumulate (MAC) functions.

Note also that the sign-magnitude logic (LOGIC₂₀) block can be sharedbetween plurality XD_(i)I_(o) channels by inserting a plurality oflatches (to store the x and y digital input words) between the LOGIC₂₀block outputs and the plurality of current switches of the respectiveplurality of iDACx₂₀ and iDACy₂₀ pairs, which also saves silicon area.

Moreover, additional area is save by utilizing only one RBN₂₀ that isshared with a plurality of XD_(i)Io₂₀, wherein the multiplier powersupply desensitization method (or XPSR method) is utilized tosubstantially desensitize each of the XD_(i)Io₂₀'s output currents toV_(DD) variations, while the chip area attributed to each of theXD_(i)Io₂₀ is reduced by eliminating the cascoded FETs from the currentreference network of each of the iDACx₂₀ and iDACy₂₀ pairs. The XPSRmethod is described next.

The multiplier power supply desensitization method substantiallydesensitizes a multiplier from power supply variations by arranging afirst ratio relationship between the first input (I_(Y)) and thereference input (I_(R)) to a multiplier wherein the I_(Y) and the I_(R)both have a substantially equivalent first dependence error (e_(dd)) topower supply variations (ΔV_(DD)) and wherein the e_(dd) cancel eachother out due to the first ratio (I_(Y)/I_(R)) relationship in amultiplier. Moreover, multiplier power supply desensitization methodsubstantially desensitizes the multiplier from ΔV_(DD) by arranging asecond ratio (I_(O)/I_(X)) relationship between the output (I_(O)) andthe second input (I_(X)) of the multiplier wherein the I_(O) and theI_(X) of the multiplier both have a substantially equivalent seconddependence error (e′_(dd)) to ΔV_(DD) and wherein the e′_(dd) canceleach other out due to the I_(O)/I_(X) relationship. Also, theI_(Y)/I_(R) is substantially equalized to I_(O)/I_(X) in the multiplier,and the e_(dd) and the e′_(dd) may be substantially equal or differentfrom one another. This means that for example e_(dd) can be zero meaningI_(Y) and I_(R) have no dependence to power supply variations, and wheree′_(dd) can be finite meaning I_(O) and I_(X) have dependence to powersupply variations, and vice versa. Moreover, for example, e_(dd) ande′_(dd) can be zero meaning that I_(Y), I_(R), I_(O), and I_(X) do nothave dependence to power supply variations.

Another way of describing the multiplier power supply desensitization(XPSR) method is as follows: An analog multiplier input-output transferfunction is I_(O)=I_(X)×I_(Y)/I_(R) or I_(O)/I_(X)=I_(Y)/I_(R), where Xis x-input current, I_(Y) is y-input current, I_(R) is a reference inputcurrent representing the full scale of I_(X) and I_(Y), and I_(O) is themultiplier's output current. The multiplier power supply desensitizationmethod arranges a multiplier where t_(o) and I_(x) can have similardependence (error) on power supply (V_(DD)), and I_(Y) and I_(R) canhave with other similar dependence (error) on V_(DD). In other words,I_(O)=i_(o) (1±e_(dd)), I_(X)=i_(x) (1±e_(dd)), I_(Y)=i_(y) (1±e′_(dd)),and I_(R)=i_(r) (1±e′_(dd)), wherein ±e_(dd) is the scale errorattributed to V_(DD) variations for i_(o) and i_(x), and ±e′_(dd) is thescale error attributed to V_(DD) variations for i_(y) and i_(r). Assuch, a scale error term (1±e_(dd)) attributed to V_(DD) variations iscanceled out in the ratio of I_(O)/I_(X). Similarly, a scale error terms(1±e′_(dd)) attributed to V_(DD) variations are canceled out in theratio of I_(Y)/I_(R). Also, note that ±e_(dd) can be the same as ordifferent from ±e′_(dd).

First, the XPSR method to help substantially desensitize a XD_(i)I_(o)from the dependence error of I_(Y)/I_(R) on power supply variations isdescribed. Let's arrange the iDACy₂₀'s current switches (comprising ofN4 y′ ₂₀ through N1 y′ ₂₀ and N4 y″ ₂₀ through N1 y″ ₂₀) with low onresistance. Also, let's arrange V1 y ₂₀=V_(DD)−Vgs_(PMOS) (e.g., placinga diode connected FET between V_(DD) and V1 y ₂₀, which can help loweriDAC's glitch and improves settling time). One of the current outputs(Iy₂₀) of iDACy₂₀ that is coupled with the y-input port of iMULT₂₀ has abias voltage of V_(DD) minus a PMOS's gate-to-source voltage (V_(gs) ofPyM₂₀). Thus, the drain-to-source voltage (V_(DS)) of FETs in thecurrent reference network of iDACy₂₀ (comprising of N4 y ₂₀ through N1 y₂₀) is V_(DD)−V_(gs). Be mindful that early voltage (V_(A)) in FETs cancause I_(DS) dependence (error) on power supply variations, wherein suchI_(DS) dependence (error) can be reduced by cascading FETs at theexpense of increasing silicon area. Accordingly, the iMULT₂₀'s currentinput Iy₂₀ is arranged in this disclosure to have a dependence error asa function of V_(DD) variations. Similarly, the reference current input(Ir₂₀) of iMULT₂₀ that is supplied by an NMOS (i.e., NrM₂₀) has a V_(DS)that is also V_(DD) minus V_(gs) of PrM₂₀. As such, the current inputthat is Ir₂₀ of iMULT₂₀ is arranged to have a substantially similardependence error as a function of V_(DD) variations to that of Iy₂₀.Hence, the I_(Y) and I_(R) have the same depended error on V_(DD)variations that is substantially rejected, without the need for cascodeFETs (which saves silicon area) in light of iMULT₂₀ ratio relationshipbetween them that is I_(Y)/I_(R).

Next, the XPSR method to help substantially desensitize a XD_(i)I_(o)from the dependence error of I_(O)/I_(X) on power supply variations isdescribed. Similar to the y-channel, let's arrange the iDACx₂₀'s currentswitches (comprising of N4 x′ ₂₀ through N1 x′ ₂₀ and N4 x″ ₂₀ throughN1 x″ ₂₀) with low on resistance. Similarly, let's arrange V1 x₂₀=V_(SS)+Vgs_(NMOS) (which can help lower iDAC's glitch and improvessettling time). One of the current outputs (Ix₂₀) of iDACx₂₀ that iscoupled with the x-input port of iMULT₂₀ has a bias voltage of V_(SS)plus a NMOS's gate-to-source voltage (V_(gs) of NxM₂₀). Thus, thedrain-to-source voltage (V_(DS)) of FETs in the current referencenetwork of iDACx₂₀ (comprising of N4 x ₂₀ through N1 x ₂₀) isV_(SS)+V_(gs). As such, the iMULT₂₀'s current input that is Ix₂₀ isarranged in this disclosure to have a dependence error as a function ofV_(SS) variations. By biasing Vxy₂₀=V_(SS)+Vgs_(NMOS), then depending onsign (or MSB) of the x or y digital input word, the bias voltage of thecurrent input (Io₂₀) of iMULT₂₀ would be subject to either V_(g), ofNoM₂₀ or that of NoM′₂₀, which are both NMOS. Thus, the iMULT₂₀'scurrent output that is Io₂₀ is arranged in this disclosure to have thesame dependence error as a function of V_(SS) variations to that ofIx₂₀. Hence, the I₀ and I_(x) have the same depended error (on V_(SS)variations) that is substantially rejected in light of iMULT₂₀ ratiorelationship between them that is I_(O)/I_(X).

Bear in mind that for machine learning applications where plurality (orsea) of XD_(i)I_(O) channels are required, the reference bias network(RBN) and LOGIC sections can be shared amongst plurality (or sea) ofXD_(i)I_(O) channels. The iDAC's current reference network can providebinary weighted currents without requiring the current sources to besized in binary weighted arrangement which saves significant area ineach iDAC utilized in XD_(i)I_(O). Further area savings are realized byeliminating the cascoded FETs from the current (mirror) referencenetwork of each iDAC utilized in XD_(i)I_(O), while utilizing the PSRmethod substantially desensitizes the XD_(i)I_(O) from power supplyvariations.

Each XD_(i)I_(O) is substantially desensitized from power supplyvariations by utilizing the multiplier power supply desensitizationmethod which is indicated by SPICE circuit simulations of FIG. 29. TheFIG. 29 simulations results are that of a XD_(i)I_(O) similar to FIG. 20circuit with a resolution of 8-bits digital words instead of that ofFIG. 20 with a resolution of 4-bits digital words. A XD_(i)I_(O) of FIG.29 is inputted with an 8-bit (x-word digital input) by an 8-bit (y-worddigital input) wherein the x and y words are ramped from zero-scale tofull scale where power supply V_(DD) is varied from 2.2V to 0.8V. FIG.29 illustrates a waveform plot that is the error curve (output currentsimulation minus output current ideal) attributed to I_(o) of theXD_(i)I_(O) indicating less than ±0.5% error in DNL (differentialnon-linearity), INL (integral non-linearity), and GE (gain-error).

In summary, some of the benefits of the embodiment disclosed in FIG. 20are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the disclosed embodiment benefits from savings in silicon diearea, lower glitch, and faster speed when plurality of XD_(i)I_(O) arerequired (e.g., in machine learning applications where 1000s ofXD_(i)I_(O) may be needed) by utilizing the multiple iDAC method that isdisclosed in section 19.

Third, the disclosed embodiment benefits from further saving in silicondie area as well as desensitization to power supply variations for eachXD_(i)I_(O) by utilizing the multiplier power supply desensitizationmethod, which also facilitates the elimination of the cascoded FETs iniDACs current reference network.

Section 21—Description of FIG. 21

FIG. 21 is a simplified circuit schematic illustrating an embodiment fora plurality-channels of mixed-mode digital-input toanalog-current-output multiplier (XD_(i)I_(O)) that is single-quadrant,wherein the XD_(i)I_(O) utilizes the multiple-channel data-convertermethod. The XD_(i)I_(O) of FIG. 21 (XD_(i)I_(O) ₂₁ ) utilizes anotherembodiment of the multiple-channel data-converter method disclosed insection 19 of this disclosure to save silicon area and improve iDAC'sdynamic performance. The XD_(i)I_(O) ₂₁ also utilizes another embodimentof the multiplier power supply desensitization method that substantiallydesensitize XD_(i)I_(O)'s output current from power supply variations,while eliminating cascodes from current sources (which saves area).

For descriptive clarity and illustrative simplicity, the embodiment ofthe XD_(i)I_(O) ₂₁ that is depicted in FIG. 21 is a single channelmultiplier with 3-bits (x-word digital input) by 3-bits (y-word digitalinput) of resolution wherein the x and y words are in binary format, butthe digital input resolutions can be higher (e.g., 6-bits to 12-bits)and plurality of channels can be in the 1000s. Let's assume theiDACy₂₁'s current switches (comprising of N4 y′ ₂₁ through N1 y′ ₂₁ andN4 y″ ₂₁ through N1 y″ ₂₁) and the iDACx₂₁'s current switches(comprising of N4 x′ ₂₁ through N1 x′ ₂₁ and N4 x″ ₂₁ through N1 x″ ₂₁)have low on resistances. Also, let's arrange V1 xy ₂₁=V_(DD)−Vgs_(PMOS)(e.g., placing a diode connected FET between V_(DD) and Vxy₂₁, which canhelp lower iDAC's glitch and improves settling time). Moreover, let'sassume that V_(GS) _(p) >>V_(DS) of PxoM₂₁ and PyrM₂₁, wherein V_(GSp)is gate-to-source voltage of a PMOS operating at full-scale current iniMULT₂₁,

As asserted earlier, XD_(i)I_(O) ₂₁ embodiment utilizes themultiple-channel method data-converter wherein a reference bias network(RBN₂₁) circuit generates a sequence of reference bias currents that aremirrored onto a respective plurality of iDAC's current referencenetworks, which is described in section 19. The same RBN₂₁ circuit canbe utilized to mirror a fixed reference current (Ir₂₁) programmed at thefull-scale of Ix₂₁ and Iy₂₁.

The XD_(i)I_(O) ₂₁ is comprising of iDACx₂₁ that generates an Ix₂₁, andiDACy₂₁ that generates an Iy₂₁, wherein Ix₂₁, Iy₂₁, and a referencecurrent (Ir₂₁) are inputted to a current multiplier or iMULT₂₁. Theresultant analog output product of iMULT₂₁ is IoM₂₁=Io₂₁ which is asingle-quadrant current output.

Note that Ix₂₁ as output of iDACx₂₁ is coupled with x-input of iMULT₂₁that is biased at about V_(DD)−V_(GSp) where V_(GSp) is that of PxoM₂₁.Similarly, Iy₂₁ as output of iDACy₂₁ is coupled with y-input of iMULT₂₁that is also biased at about V_(DD)−V_(GSp) where V_(GSp) is that ofPyM₂₁. Also, Ir₂₁ provided by NrM₂₁ is coupled with reference currentinput of iMULT₂₁ that is also biased at about V_(DD)−V_(GSp) whereV_(GSp) is that of PrM₂₁.

As stated earlier, the XD_(i)I_(O)'s dynamic performance is improved andsilicon area is reduced by utilizing the multiple-channel data-convertermethod that is described in section 19 of this disclosure. A single biasreference network (RBN₂₁) is shared by biasing a plurality XD_(i)I_(O)channels, wherein each XD_(i)I_(O) is comprising of iMULT (e.g., aniMULT₂₁) and pair of iDACs (e.g., iDACx₂₁ and iDACy₂₁). Here,substantially equal 1x sized current sources in the iDAC's referencecurrent network is biased separately by RBN₂₁ wherein each iDAC's 1xsized current source carries its respective binary weighted current.

Due to FET's early voltage (V_(A)), the I_(DS) of a current source madeof one FET increases with increasing its V_(DS). As such I_(DS) of acurrent source FET is sensitive to V_(DD) variation, unless the currentsource is cascoded (to increase the FET's output impedance) which takesdouble the area for a given current source. The multiple-channeldata-converter method of section 19 is combined with the XPSR methodthat was described in section 20, in order to (1) avoid the cascodedFETs, (2) substantially desensitize the multiplier from power supplyvariations, (3) reduce the size of iDAC's binary weighted currentreference network. Such combination of methods is utilized in theembodiment of a RBN₂₁ & PSR₂₁ circuit, wherein the RBN₂₁ & PSR₂₁ circuitis shared with a plurality of XD_(i)I_(O) ₂₁ channels.

Notice that the PSR circuit is comprised of identical sections that arerepeated for each sequence of reference bias currents of RBN, and thateach multiplier XD_(i)I_(O21) channel is comprised of iDACx₂₁, iDACy₂₁,and an iMULT₂₁.

For example, the PSR₂₁ section of the MSB current of RBN₂₁ is comprisingof P4 c ₂₁, P4 c′ ₂₁, P4 c″ ₂₁, N4 c ₂₁, and N4 c′ ₂₁. The MSB currentof the RBN₂₁ circuit, which is set by the I_(DS) of N4 r ₂₁, is mirroredthrough P4 c ₂₁ and the diode connected P4 c′ ₂₁ where P4 c″ ₂₁regulates the current in N4 c′ ₂₁ and its diode connected N4 c ₂₁ mirrorwhile keeping the V_(GS) of P4 c ₂₁ and P4 c′ ₂₁ substantiallyequalized. The V_(as) of N4 c′ ₂₁ is V_(DD)−V_(GSp) with V_(GSp) beingthat of P4 c′ ₂₁. The PSR₂₁ section's regulation of the MSB current ofRBN₂₁ kicks in when, for example, V_(DD) falls then I_(DS) of P4 c″ ₂₁increases which raises the operating current in N4 c ₂₁, N4 c′ ₂₁, P4 c′₂₁, and P4 c ₂₁ until the I_(DS) of P4 c ₂₁ is substantially equalizedwith I_(DS) of N4 r′ ₂₁, which is independent of V_(DD) variations(since I_(DS) of N4 r′ ₂₁ mirrors a multiple of the fixed referencecurrent Ir′₂₁).

In other words, when V_(DD) varies, the I_(DS) of N4 c′ ₂₁ and P4 c′ ₂₁is regulated and independent of V_(DD) variations, despite N4 c′ ₂₁'sV_(DS)=V_(DD)−V_(GSp) The V4 r ₂₁ that is the V_(GS) of N4 c ₂₁ and N4c′ ₂₁ programs the bus voltage that is coupled with the gate terminalsof N4 y ₂₁ and N4 x ₂₁ which are the MSB current sources of the currentreference network of iDACx₂₁ and iDACy₂₁. Considering that the biasvoltage at the drain terminals of N4 y ₂₁ and N4 x ₂₁ are coupled withthe inputs of iMULT₂₁ which are about V_(DD)−V_(GSp), the I_(DS) of theN4 y ₂₁ and N4 x ₂₁ is also independent of V_(DD) variations becausethey mirror N4 c ₂₁ and N4 c′ ₂₁.

Be mindful that the drain terminals of N4 x ₂₁ and N4 y ₂₁ (whenselected in iDACs) are coupled with the x and y analog input currentports of iMULT₂₁, respectively, whose bias voltages are arranged asV_(GSp) of PxoM₂₁ and PyM₂₁. In summary, the MSB current sources ofiDAC's current reference networks are arranged to be independent ofV_(DD) variations, without cascoded FETs in iDAC's current referencenetwork, and with the iDAC's binary weighted current reference networkthat is not sized in a binary weighted manner, combination of whichsaves substantial silicon area (especially in machine learningapplications where 1000s of iDACs may be required).

Note that the same description as above is applicable to N2 r ₂₁, N2 r′₂₁ and N1 r ₂₁, N1 r′ ₂₁ that in conjunction with the regulatingmechanism of their respective PSR₂₁ sections, generate the V2 r ₂₁ andV1 r ₂₁ bus voltages.

Thus, V2 r ₂₁ that is the V_(GS) of N2 c ₂₁ and N2 c′ ₂₁ is the busvoltage that is coupled with the gate terminals of N2 y ₂₁ and N2 x ₂₁which can be referred to as the second bit current sources of currentreference network of iDACx₂₁ and iDACy₂₁. The I_(DS) of N2 y ₂₁ and N2 x₂₁ is also independent of V_(DD) variations, without cascoded FETs, asexplained above.

Similarly, V1 r ₂₁ that is the V_(GS) of N1 c ₂₁ and N1 c′ ₂₁ is the busvoltage that is coupled with the gate terminals of N1 y ₂₁ and N1 x ₂₁which are the LSB current sources of current reference network ofiDACx₂₁ and iDACy₂₁. Accordingly, I_(DS) of N1 y ₂₁ and N1 x ₂₁ isindependent of V_(DD) variations, without cascoded FETs. As indicatedearlier, V4 r ₂₁, V2 r ₂₁, and V1 r ₂₁ are bus voltages in the referencebias network (RBN) that set the sequence of reference bias currents forplurality of iDACs (e.g., there can be 1000s if iDACs sharing thesequence bus voltages generated by the same RBN).

In summary, the sequence of reference bias currents generated in the RBNcircuit are substantially desensitized from V_(DD) variations by the PSRcircuit before they are mirrored onto the iDAC's current referencenetworks. As such, iDAC's output currents are arranged to be independentof V_(DD) variations, without cascoded FETs in iDAC's current referencenetwork which save silicon area.

As presented in section 20, the iMULT₂₁'s input output transfer functionfollows the Iy₂₁/Ir₂₁=Io₂₁/Ix₂₁ relationship. The Iy₂₁/Ir₂₁ issubstantially desensitized to V_(DD) variations, since iDACy₂₁ currentoutput that is Iy₂₁ and Ir₂₁ are substantially desensitized to V_(DD)variations without cascoded FETs, as explained earlier.

The iDACx₂₁ current output is also substantially desensitized to V_(DD)variations without cascoded FETs. The PoM₂₁ is cascoded with PoM′₂₁ toincrease the output impedance of output port of iMULT₂₁ andsubstantially desensitized Io₂₁ to V_(DD) variations. Also, PxM₂₁ iscascoded with PxM′₂₁ to help match the V_(DS) of PxM₂₁ and PoM₂₁, whichhelps with Io₂₁/Ix₂₁ insensitivity to V_(DD) variations.

Each XD_(i)I_(O) is substantially desensitized from power supplyvariations by utilizing another embodiment of the multiplier powersupply desensitization method that is indicated by SPICE circuitsimulations of FIG. 28. It is the simulations results of a XD_(i)I_(O)similar to that of FIG. 21, but with a resolution of 8-bits digitalwords instead of that of FIG. 21 with a resolution of 3-bits digitalwords. A XD_(i)I_(O) of FIG. 29 is inputted with an 8-bit (x-worddigital input) by an 8-bit (y-word digital input) wherein the x and ywords are ramped from zero-scale to full scale where power supply V_(DD)is varied from 2.2V to 0.8V. FIG. 28 illustrates a waveform plot that isthe error curve (output current simulation minus output current ideal)attributed to I_(O) of the XD_(i)I_(O) indicating less than ±0.75% errorin DNL (differential non-linearity), INL (integral non-linearity), andGE (gain-error).

In summary some of the benefits of the embodiment disclosed in FIG. 21are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the disclosed embodiment benefits from savings in silicon diearea, lower glitch, and faster speed when plurality of XD_(i)I_(O) arerequired (e.g., in machine learning applications where 1000s ofXD_(i)I_(O) may be needed) by utilizing the multiple iDAC method that isdisclosed in section 19.

Third, the disclosed embodiment benefits from further saving in silicondie area as well as desensitization to power supply variations for eachXD_(i)I_(O) by utilizing another embodiment of the multiplier powersupply desensitization method, which also facilitates the elimination ofthe cascoded FETs in iDACs current reference network.

Section 22A—Description of FIG. 22A

FIG. 22A is a SPICE circuit simulations that illustrates the linearityerror in % between an ideal output current (Io_(ideal)) iDAC versus thesimulated output current (Io_(simulation)) of one of the iDAC channelsas arranged similar to that of FIG. 19 but with an 8-bit resolution. Thereference bias network is not trimmed here.

Keeping in mind that 8-bit of resolution computes to about ±0.4% ofaccuracy, FIG. 22 indicates DNL (differential non-linearity) and INL(integral non-linearity) of less than about ±0.5%. Note that the iDAC'sdigital input word span between zero and full scale.

Section 22B—Description of FIG. 22B

FIG. 22B is a SPICE circuit simulations that illustrates the linearityerror in % between an ideal output current (Io_(ideal)) iDAC versus thesimulated output current (Io_(simulation)) of one of the iDAC channelsas arranged similar to that of FIG. 19 but with an 8-bit resolution. Thetwo MSBs of the reference bias network (RBN) is trimmed here, whichwould improve the linearity of plurality of iDACs (that are biased fromthe same RBN).

Keeping in mind that 8-bit of resolution computes to about ±0.4% ofaccuracy, FIG. 22 indicates DNL (differential non-linearity) and INL(integral non-linearity) of less than about ±0.25% which is roughly afactor of 4 improvement. Note that the iDAC's digital input word spanbetween zero and full scale.

Section 23—Description of FIG. 23

FIG. 23 is a simplified circuit schematic illustrating an embodiment ofa digital-input to analog-current-output multiplier (XD_(i)I_(O)) thatoperate in current mode comprising of an iDACx₂₃ whoseanalog-current-output supplies the reference input to an iDACy₂₃.

For descriptive clarity and illustrative simplicity, the XD_(i)I_(O) ₂₃'s resolution is arranged as a 3-bit (x-channel for iDACx₂₃) by 3-bit(y-channel for iDACy₂₃), but the resolution can be higher (e.g.,16-bits).

A current reference (Ir′₂₃) is inputted and mirrored onto iDACx₂₃'sbinary weighed current reference network comprising of P4 x ₂₃ (scaledat 4×), P2 x ₂₃ (scaled at 2×), and P1 x ₂₃ (scaled at 1×). TheiDACx₂₃'s digital inputs (Dx₂₃ digital word) are D3 x ₂₃ (as MSB)through D1 x ₂₃ (as LSB), which control iDACx₂₃'s analog currentswitches P4 x′ ₂₃ through P1 x′ ₂₃ and P4 x″ ₂₃ through P1 x″ ₂₃.

The selected sums of iDACx₂₃'s analog current switch outputs are steeredthrough node n₂₃ onto the reference input of iDACy₂₃.

The iDACy₂₃'s binary weighed current reference network comprising of P4y ₂₃ (scaled at 4×), P2 y ₂₃ (scaled at 2×), and P1 y ₂₃ (scaled at 1×)have their source terminals coupled together and floating on node n₂₃.Moreover, note that the gate terminal of P4 y ₂₃, P2 y ₂₃, and P1 y ₂₃are coupled together with Pr′₂₃'s cascode bias voltage Vy′₂₃, whichprovides enough headroom for the iDACx₂₃'s binary weighed currentreference network and improves its output impedance. Similarly, theiDACy₂₃'s digital inputs (Dy₂₃ digital word) are D3 y ₂₃ (as MSB)through D1 y ₂₃ (as LSB) control iDACy₂₃'s analog current switches P4 y′₂₃ through P1 y′ ₂₃ and P4 y″ ₂₃ through P1 y″ ₂₃. The selected sums ofiDACy₂₃'s analog current switch outputs are steered through theXD_(i)I_(O) ₂₃ s current-output node Io₂₃ that generates the analogcurrent product Ax₂₃×Ay₂₃/Ar₂₃, wherein Ax₂₃ is the analog currentrepresentation of the digital word Dx₂₃, Ay₂₃ is the analog currentrepresentation of the digital word Dy₂₃, and Ar₂₃ is a multiple ofIr′₂₃.

The disclosed XD_(i)I_(O) ₂₃ benefits from current mode operations,which has been discussed in this disclosure. Another benefit ofXD_(i)I_(O) ₂₃ disclosure results from feeding the current output of afirst iDAC directly into the reference port of a second iDAC, whosereference input port is floating. The floating iDAC method (that isutilized here) was describe in section 1 of this disclosure. Here, thesource terminals of current reference FET network of the second iDAC arecoupled together to arrange the floating reference port of the secondiDAC. As such, a current mirror (to channel the first iDAC outputcurrent onto the second iDAC reference input port) is avoided, whichsaves area and improves accuracy since it avoids the mismatch associatedwith the said current mirror.

Section 24—Description of FIG. 24

FIG. 24 is a simplified circuit schematic illustrating anotherembodiment of mixed-mode digital-input to analog-current-outputmultiplier (XD_(i)I_(O)) that operate in current mode comprising of aniDACx₂₄ whose analog-current-output supplies the reference input to aniDACy₂₄.

For descriptive clarity and illustrative simplicity, the XD_(i)I_(O) ₂₄'s resolution is arranged as a 3-bit (x-channel for iDACx₂₄) by 3-bit(y-channel for iDACy₂₄) but the resolution can be higher (e.g.,16-bits).

A current reference (Ir′₂₄) is inputted and mirrored onto iDACx₂₄'sbinary weighed current reference network comprising of P4 x ₂₄ (scaledat 4×), P2 x ₂₄ (scaled at 2×), and P1 x ₂₄ (scaled at 1×). TheiDACx₂₄'s digital inputs (Dx₂₄ digital word) are D3 x ₂₄ (as MSB)through D1 x ₂₄ (as LSB), which control iDACx₂₄'s analog currentswitches P4 x′ ₂₄ through P1 x′ ₂₄ and P4 x″ ₂₄ through P1 x″ ₂₄.

Note that the embodiment of FIG. 24 does not arrange iDACx₂₄'s analogcurrent switches is series with the binary weighed current referencenetwork path. Instead, iDACx₂₄'s analog current switches are enabled(turned on) by switch coupling with the gate terminal of Pr₂₄ ordisabled (turned off) by switch coupling with V_(DD). For example, whenD3 x ₂₄ digital value is high (on), then the analog current switch P4 x′₂₄ is on and the analog current switch P4 x″ ₂₄ is off, which causes P4x ₂₄'s binary weighted MSB current (scaled and mirrored by P4 x ₂₄-Pr₂₄current mirror) to flow onto the iDACx₂₄ current output port that isnode n₂₄. Conversely, for example, when D3 x ₂₄ digital value is low(off), then the analog current switch P4 x′ ₂₄ is off and the analogcurrent switch P4 x″ ₂₄ is on, which shuts off P4 x ₂₄ and blocks its'binary weighted MSB current from flowing onto the iDACx₂₄ current outputport that is node n₂₄. The same principle of operations applies to theother-bits of iDACx₂₄.

The selected sums of iDACx₂₄'s analog current switch outputs are steeredthrough the floating node n₂₄ and onto the reference input of iDACy₂₄.

The iDACy₂₄'s binary weighed current reference network comprising of P4y ₂₄ (scaled at 4×), P2 y ₂₄ (scaled at 2×), and P1 y ₂₄ (scaled at 1 x)have their source terminals coupled together and floating on node n₂₄.Moreover, be mindful that the gate terminal of P4 y ₂₄, P2 y ₂₄, and P1y ₂₄ are coupled together with Pr′₂₄'s cascode bias voltage Vy′₂₄, whichprovides enough headroom for the iDACx₂₄'s binary weighed currentreference network and improves its output impedance. Similarly, theiDACy₂₄'s digital inputs (Dy₂₄ digital word) are D3 y ₂₄ (as MSB)through D1 y ₂₄ (as LSB) control iDACy₂₄'s analog current switches P4 y′₂₄ through Ply′₂₄ and P4 y″ ₂₄ through Ply″₂₄. The selected sums ofiDACy₂₄'s analog current switch outputs are steered through theXD_(i)I_(O) ₂₄ 's current-output node Io₂₄ that generates the analogcurrent product Ax₂₄×Ay₂₄/Ar₂₄, wherein Ax₂₄ is the analog currentrepresentation of the digital word Dx₂₄, Ay₂₄ is the analog currentrepresentation of the digital word Dy₂₄, and Ar₂₄ is a multiple ofIr′₂₄.

The disclosed XD_(i)I_(O) ₂₄ benefits from current mode operations,which has been discussed in this disclosure. Another benefit ofXD_(i)I_(O) ₂₄ disclosure results from feeding the current output of afirst iDAC directly into the reference port of a second iDAC, whosereference input port is floating. The floating iDAC method, which isutilized here, was describe in section 1 of this disclosure. Here, thesource terminals of current reference FET network of the second iDAC arecoupled together to arrange the floating reference port of the secondiDAC. As such, a current mirror (to channel the first iDAC outputcurrent onto the second iDAC reference input port) is avoided, whichsaves area and improves accuracy since it avoids the mismatch associatedwith the said current mirror.

Section 25—Description of FIG. 25

FIG. 25 is a simplified circuit schematic illustrating anotherembodiment of a digital-input to analog-current-output multiplier(XD_(i)I_(O)) that operate in current mode. The XD_(i)I_(O) ₂₅ iscomprising of a first current-output iDACx₂₅ whose analog-current-outputsupplies the reference input to an iDACy₂₅, while a power supplydesensitization circuit (PSR₂₅) substantially desensitize theXD_(i)I_(O25)'s output current to V_(DD) variations wherein silicon areais saved by eliminating the need for cascoded FETs in the iDACs.

For descriptive clarity and illustrative simplicity, the XD_(i)I_(O25)'sresolution is arranged as a 3-bit (x-channel for iDACx₂₅) by 3-bit(y-channel for iDACy₂₅) but the resolution can be higher (e.g.,16-bits).

A current reference (b-′₂₅) is inputted and mirrored onto iDACx₂₅'sbinary weighed current reference network comprising of P4 x ₂₅ (scaledat 4×), P2 x ₂₅ (scaled at 2×), and P1 x ₂₅ (scaled at 1×). TheiDACx₂₅'s digital inputs (Dx₂₅ digital word) are D3 x ₂₅ (as MSB)through D1 x ₂₅ (as LSB), which control iDACx₂₅'s analog currentswitches P4 x′ ₂₅ through P1 x′ ₂₅ and P4 x″ ₂₅ through P1 x″ ₂₅.

Be mindful that generally cascoded FETs are utilized in an iDAC'scurrent reference network to increase its output impedance andsubstantially desensitize an iDAC's output current from power supplyvariations.

Here, the selected sums of iDACx₂₅'s analog current switch outputs aresteered through node n₂₅ onto a power supply desensitization circuit(PSR₂₅). One of the objectives of PSR₂₅ is to substantially desensitizethe output current of XD_(i)I_(O) ₂₅ from power supply variations,wherein the cascode FETs are eliminated from the binary weighted currentreference network of iDACx₂₅ and iDACy₂₅. Without the cascode FETs, thebinary weighted current reference network net-net area is reducedsubstantially compared to the added area of PSR₂₅ (and hence the overallarea of XD_(i)I_(O) ₂₅ is reduced).

In the disclosed embodiment of FIG. 25, the PSR₂₅ receives the iDACx₂₅output current at node n₂₅ whose DC voltage is biased at V_(DD)−VGS_(Pq)₂₅ . As such the binary weighted current reference network output ofiDACx₂₅ (at node n₂₅) tracks the Ir′₂₅ (that is a fixed referencecurrent and independent of V_(DD) by design), wherein iDACx₂₅ outputport is also biased at V_(DD)−VGS_(Pr) ₂₅ , which substantiallydesensitizes iDACx₂₅'s output current from V_(DD) variations. Withoutthe PSR₂₅ and without the cascoded FETs, the iDACy₂₅'s output currentwould vary with V_(DD) since the drain-to-source voltage (V_(DS)) ofiDACy₂₅'s binary weighted current reference network (N4 y ₂₅, N2 y ₂₅,and N1 y ₂₅) is subject to V_(DD) variations and the DC bias voltage ofIO₂₅ port (e.g., V_(IO) ₂₅ =V_(DD)−V_(GS)). Notice that the V_(DS) ofPq′₂₅ is V_(DD)−VGS_(Nq) ₂₅ and V_(DS) of Nq′₂₅ is V_(DD)−VGS_(Pq) ₂₅ .To substantially desensitize the output current of iDACy₂₅ (without its'cascoded FETs), Pq′₂₅ regulates the current through Nq₂₅ and Nq′₂₅ untilI_(DS) of Nq′₂₅ and the output current of iDACx₂₅ (flowing through noden₂₅) are substantially equalized. The I_(DS) of Nq′₂₅ is mirrored ontothe current reference network of iDACy₂₅ (stripped from cascoded FETs tosave area), and accordingly the current output of iDACy₂₅ which is theanalog current output of D_(i)I_(O) ₂₅ is substantially desensitizedfrom V_(DD) variations.

The iDACy₂₅'s binary weighed current reference network comprising of N4y ₂₅ (scaled at 4×), N2 y ₂₅ (scaled at 2×), and N1 y ₂₅ (scaled at 1 x)are scaled and mirrored to I_(DS) of Nq′₂₅, and Nq₂₅. Here also, theiDACy₂₅'s digital inputs (Dy₂₅ digital word) are D3 y ₂₅ (as MSB)through D1 y ₂₅ (as LSB) control iDACy₂₅'s analog current switches N4 y′₂₅ through N1 y′ ₂₅ and N4 y″ ₂₅ through N1 y″ ₂₅. The selected sums ofiDACy₂₅'s analog current switch outputs are steered through theXD_(i)I_(O) ₂₅ 's current-output node IO₂₅. The iDACy₂₅'s outputgenerates the equivalent analog output current product Ax₂₅×Ay₂₅/Ar₂₅,wherein Ax₂₅ is the analog current representation of the digital wordDx₂₅, Ay₂₅ is the analog current representation of the digital wordDy₂₅, and Ar₂₅ is a scaled Ir′₂₅. Again, consider that node IO₂₅ can bebiased at a V_(GS) below V_(DD).

The disclosed XD_(i)I_(O) ₂₅ benefits from current mode operations,which has been discussed in this disclosure. Another benefit ofXD_(i)I_(O) ₂₅ is having a smaller area by utilizing a method ofrejecting power supply variations by regulating the first iDAC's outputcurrent before it is fed onto the reference input the second iDAC,wherein the iDAC's current reference networks are stripped from cascodedFETs. This power supply desensitization method utilized in XD_(i)I_(O)₂₅ (via the embodiment of a power supply desensitization circuit PSR₂₅)substantially desensitizes XD_(i)I_(O) ₂₅ 's output from V_(DD)variations, wherein the cascoded FETs (in the iDAC's current referencenetworks) are eliminated, which saves silicon area and lowers cost.

Section 26—Description of FIG. 26

FIG. 26 is a simplified circuit schematic illustrating anotherembodiment of a digital-input to analog-current-output multiplier(XD_(i)I_(O)) that operate in current mode. The XD_(i)I_(O) ₂₆ iscomprising of an iDACx₂₆ whose analog-current-output supplies thereference input to a power supply desensitization circuit (PSR₂₆) thatbiases the current reference network of the iDACy₂₆. Here, PSR₂₆substantially desensitize the XD_(i)I_(O) ₂₆ 's output current to V_(DD)variations, while the iDAC's current reference network areas are reducedby eliminating the cascoded FETs.

For descriptive clarity and illustrative simplicity, the XD_(i)I_(O) ₂₆'s resolution is arranged as a 3-bit (x-channel for iDACx₂₆) by 3-bit(y-channel for iDACy₂₆) but the resolution can be higher (e.g.,16-bits).

A current reference (b-′₂₆) is inputted and mirrored onto iDACx₂₆'sbinary weighed current reference network comprising of P4 x ₂₆ (scaledat 4×), P2 x ₂₆ (scaled at 2×), and P1 x ₂₆ (scaled at 1×). TheiDACx₂₆'s digital inputs (Dx₂₆ digital word) are D3 x ₂₆ (as MSB)through D1 x ₂₆ (as LSB), which control iDACx₂₆'s analog currentswitches P4 x′ ₂₆ through P1 x′ ₂₆ and P4 x″ ₂₆ through P1 x″ ₂₆.

The selected sums of iDACx₂₆'s analog current switch outputs are steeredthrough node n₂₆ onto a power supply desensitization circuit (PSR₂₆).Similar to the disclosure in section 25, one of the objectives of PSR₂₆is to substantially desensitize the output current of DD_(i)I_(O) ₂₆from power supply variations, while the cascode FETs are eliminated fromthe binary weighted current reference network of iDACx₂₆ and iDACy₂₆. Byeliminating the cascode FETs from the binary weighted current referencenetwork, net-net the area of iDACx₂₆ and iDACy₂₆ is substantiallyreduced compared to the added area of PSR₂₆ (and hence the overall areaof XD_(i)I_(O) ₂₆ is reduced).

Consider that cascoded FETs may be needed in an iDAC's current referencenetwork to increase its output impedance and substantially desensitizean iDAC's output current from power supply variations. Here, the PSR₂₆receives the iDACx₂₆ output current at node n₂₆ whose DC voltage isbiased at V_(DD)−V_(GS) _(P) wherein V_(GS) _(P) is that of Pq₂₆. TheIr′₂₆ (that is independent of V_(DD) by design) is biased atV_(DD)−VGS_(Pr) ₂₆ where Ir′₂₆'s current biases the binary weightedcurrent reference network of iDACx₂₆. As such, the reference currentinput port and the current output (at node n₂₆) of iDACx₂₆ are biased atV_(DD)−V_(GS) _(P) and track each other, which therefore helps iDACx₂₆output current to be substantially desensitized from V_(DD) variations.

Moreover, keep in mind that without the PSR₂₆ and without the cascodedFETs, the iDACy₂₆'s output current would also vary with V_(DD) since thedrain-to-source voltage (V_(DS)) of iDACy₂₆'s binary weighted currentreference network (N4 y ₂₆, N2 y ₂₆, and N1 y ₂₆) is subject to V_(DD)variations and the DC bias voltage of IO₂₆ port (e.g.,V₁₀₂₆=V_(DD)−V_(GS)). Note that the V_(DS) of Pq″₂₆ is V_(DD)−VGS_(Nq)₂₆ and V_(DS) of Nq₂₆ is V_(DD)−VGS_(Pq) ₂₆ . As such, to substantiallydesensitize the output current of iDACy₂₆ (without cascoded FETs), theinverting current amplifier comprising of Pq₂₆, Pq′₂₆, and Pq″₂₆regulates the currents through Nq″₂₆ and Nq₂₆ until I_(DS) of Nq₂₆ andthe output current of iDACx₂₆ (flowing through node n₂₆) aresubstantially equalized. The I_(DS) of Nq″₂₆ and Nq₂₆ are mirrored ontothe current reference network of iDACy₂₆ (stripped from cascoded FETs tosave area), and accordingly the current output of iDACy₂₆ that is theanalog current output of XD_(i)I_(O) ₂₆ is substantially desensitizedfrom V_(DD) variations.

The iDACy₂₆'s binary weighed current reference network comprising of N4y ₂₆ (scaled at 4×), N2 y ₂₆ (scaled at 2×), and N1 y ₂₆ (scaled at 1 x)are scaled and mirrored to I_(DS) of Nq″₂₆, Nq₂₆. Here also, theiDACy₂₆'s digital inputs (Dy₂₆ digital word) are D3 y ₂₆ (as MSB)through D1 y ₂₆ (as LSB) control iDACy₂₆'s analog current switches N4 y′₂₆ through N1 y′ ₂₆ and N4 y″ ₂₆ through N1 y″ ₂₆. The selected sums ofiDACy₂₆'s analog current switch outputs are steered through theXD_(i)I_(O) ₂₆ 's current-output node IO₂₆ that generates the equivalentanalog output current product Ax₂₆×Ay₂₆/Ar₂₆, wherein Ax₂₆ is the analogcurrent representation of the digital word Dx₂₆, Ay₂₆ is the analogcurrent representation of the digital word Dy₂₆, and Ar₂₆ is a scaledIr′₂₆. Again, notice that node IO₂₆ can be biased at a V_(GS) belowV_(DD).

The disclosed XD_(i)I_(O) ₂₆ benefits from current mode operations,which has been discussed in this disclosure. Another benefit ofXD_(i)I_(O) ₂₆ is having a smaller area by utilizing the method ofrejecting power supply variations by regulating iDACx₂₆ output currentbefore it is fed onto the reference input of iDACy₂₆, wherein bothiDAC's binary weighted current reference networks are stripped fromcascoded FETs. The disclosed embodiment of power supply desensitizationmethod in PSR₂₆ is utilized in XD_(i)I_(O) ₂₆ which substantiallydesensitizes iDACx₂₆ output current from V_(DD) while PSR₂₆ regulatesiDACy₂₆'s reference input current. Thus, the output current of theoverall multiplier is substantially desensitized from power supplyvariations and the cascoded FETs (in both of the iDAC's currentreference networks) are eliminated which saves area and lowers cost.

Section 27—Description of FIG. 27

FIG. 27 is a simplified circuit schematic illustrating anotherembodiment of mixed-mode digital-input to analog-current-outputmultiplier (XD_(i)I_(O)) that operate in current mode comprising of afirst current-output iDAC or iDACx₂₇ whose analog-current-outputsupplies the reference input to a second current-output iDAC or iDACy₂₇.

For descriptive clarity and illustrative simplicity, the XD_(i)I_(O) ₂₇'s resolution is arranged as a 3-bit (x-channel for iDACx₂₇) by 3-bit(y-channel for iDACy₂₇), but the resolution can be higher (e.g.,16-bits).

A current reference (Ir′₂₇) is inputted and mirrored onto iDACx₂₇'sbinary weighed current reference network comprising of P4 ₂₇ (scaled at4×), P2 ₂₇ (scaled at 2×), and P1 ₂₇ (scaled at 1×). The iDACx₂₇'sdigital inputs (Dx₂₇ digital word) are D 3X₂₇ (as MSB) through D 1X₂₇(as LSB), which control iDACx₂₇'s analog current switches P4′₂₇ throughP1′₂₇ and P4″₂₇ through P1″₂₇. For example, when D3 x ₂₇ is in a lowstate, current switch P4″₂₇ turns on and all of P4 ₂₇'s current flowsthrough P4″₂₇ into Vx₂₇ (which can be coupled with V_(SS)). Conversely,when D3 x ₂₇ is in a high state, current switch P4″₂₇ turns off and allof P4 ₂₇'s current flows through P4′₂₇ into node n₂₇ (which is thecurrent output port of iDACx₂₇). Note also that gate terminals of FETscomprising of P4′₂₇ through P1′₂₇ are coupled to a fixed bias voltage(Vx′₂₇), and as such, these FETs can serve as analog current switch aswell as cascoded FETs that increase the output impedance of iDACx₂₇'scurrent reference network. The output current of iDACx₂₇ is fed ontoNy₂₇ to function in a current mirror supplying the current referenceinput of iDACy₂₇.

The iDACy₂₇'s binary weighed current reference network comprising of N4₂₇ (scaled at 4×), N2 ₂₇ (scaled at 2×), and N1 ₂₇ (scaled at 1×) arescaled and mirrored to I_(DS) of Ny₂₇. Here also, the iDACy₂₇'s digitalinputs (Dy₂₇ digital word) are D3 y ₂₇ (as MSB) through D1 y ₂₇ (as LSB)that control iDACy₂₇'s analog current switches N4′₂₇ through N1′₂₇ andN4″₂₇ through N1″₂₇. Similar to the arrangement in iDACx₂₇, here forexample, when D3 y ₂₇ is in a high state, current switch N4′₂₇ turns onand all of N4 ₂₇'s current flows through N4′₂₇ into IO₂₇ port.Conversely, when D3 y ₂₇ is in a low state, current switch N4′₂₇ turnsoff and all of N4 ₂₇'s current flows through N4″₂₇ and onto Vy₂₇ (whichcan be coupled with V_(DD)). Note also that gate terminals of FETscomprising of N4″₂₇ through N1″₂₇ are coupled to a fixed bias voltage(Vy″₂₇), and as such, these FETs serve as analog current switch as wellas cascode that increase the output impedance of iDACy₂₇'s currentreference network. The selected sums of iDACy₂₇'s analog current switchoutputs are steered through the XD_(i)I_(O) ₂₇ 's current-output nodeIO₂₇ that generates the equivalent analog output current productAx₂₇×Ay₂₇/Ar₂₆, wherein Ax₂₇ is the analog current representation of thedigital word Dx₂₇, Ay₂₇ is the analog current representation of thedigital word Dy₂₇, and Ar₂₇ is a scaled Ir′₂₇.

The disclosed XD_(i)I_(O) ₂₇ benefits from current mode operations,which has been discussed in this disclosure. Another benefit ofXD_(i)I_(O) ₂₇ is having a smaller area by utilizing the same FETs ascurrent switches of each iDAC and as cascoded FETs (to increase theiDAC's current reference network's output impedance).

Section 28—Description of FIG. 28

FIG. 28 is a circuit simulations showing the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to theoutput current (I_(o)) of a XD_(i)I_(O) that is arranged similar to thatof FIG. 21 but having an 8-bit digital inputs instead of 3-bits.

As noted, the XD_(i)I_(O) circuit (whose simulation is provided in FIG.28) is inputted with an 8-bit (x-word digital input) by an 8-bit (y-worddigital input) wherein the x and y words are ramped from zero-scale tofull scale while power supply V_(DD) is varied from 2.2V (the upperwaveform of FIG. 28) to 0.8V (the lower waveform of FIG. 28).

FIG. 28 illustrates a waveform plot that is the error curve (i.e.XD_(i)I_(O)'s output current I_(O) simulation minus XD_(i)I_(O)'s outputcurrent I_(O) ideal) indicating under ±0.75% error in DNL (differentialnon-linearity), INL (integral non-linearity), and GE (gain-error). FIG.28 indicates that the XD_(i)I_(O) with 8-bit digital inputs issubstantially desensitized from power supply variations by utilizing themultiplier power supply desensitization method.

Section 29—Description of FIG. 29

FIG. 29 is a circuit simulations showing the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to theoutput current (I_(o)) of a XD_(i)I_(O) that is arranged similar to thatof FIG. 20 but having an 8-bit digital inputs instead of 4-bits.

As noted, the XD_(i)I_(O) circuit whose simulation is provided in FIG.29 is inputted with an 8-bit (x-word digital input) by an 8-bit (y-worddigital input) wherein the x and y words are ramped from zero-scale tofull scale where power supply V_(DD) is varied from 2.2V (the upperwaveform of FIG. 29) to 0.8V (the lower waveform of FIG. 29).

FIG. 29 illustrates a waveform plot that is the error curve (i.e.XD_(i)I_(O)'s output current I_(O) simulation minus XD_(i)I_(O)'s outputcurrent I_(O) ideal) indicating under ±0.5% error in DNL (differentialnon-linearity), INL (integral non-linearity), and GE (gain-error). FIG.29 indicates that the XD_(i)I_(O) with 8-bit digital inputs issubstantially desensitized from power supply variations by utilizing themultiplier power supply desensitization method.

Section 30—Description of FIG. 30

FIG. 30 is a simplified circuit schematic illustrating anotherembodiment for a plurality-channels of mixed-mode digital-input toanalog-current-output multiplier (XD_(i)I_(O)) that is single-quadrant,wherein the XD_(i)I_(O) utilizes the multiple-channel data-convertermethod. The XD_(i)I_(O) of FIG. 30 (XD_(i)I_(O) ₃₀ ) utilizes anotherembodiment of the multiple-channel data-converter method disclosed insection 19 of this disclosure to save silicon area and improve iDAC'sdynamic performance. The XD_(i)I_(O) ₃₀ also utilizes another embodimentof the multiplier power supply desensitization method (or XPSR method)disclosed in section 20 that substantially desensitize XD_(i)I_(O)'soutput current from power supply variations, while eliminating cascodesfrom current sources (which saves area).

The overall description of XD_(i)I_(O) provided in section 21(illustrated in FIG. 21) is applicable to the XD_(i)I_(O 30) here. TheiDACs and iMULT between FIG. 21 and FIG. 30 are identical. Thus, thedescription provided in section 21 (illustrated in FIG. 21) about theiDACs is applicable to pairs of iDACx₃₀ and iDACy₃₀. Also, thedescription provided in section 21 (illustrated in FIG. 21) about theiMULT is applicable to iMULT₃₀.

The embodiment of RBN₃₀ & PSR₃₀ utilizes another combination of themultiple-channel data-converter method disclosed in section 19 and theXPSR method disclosed in section 20. In the embodiment of RBN₃₀ & PSR₃₀illustrated in FIG. 30, substantial area savings are realized byeliminating the cascode from current sources in iDACx₃₀, iDACy₃₀,iMULT₃₀, and the RBN₃₀ circuits, while the output current ofXD_(i)I_(O 30) is substantially desensitized from V_(DD) variations.This is done by regulating the reference bias currents of RBN₃₀ so thatthe outputs of iDACx₃₀ and iDACy₃₀ (which supplies a pair of the inputcurrents to iMULT₃₀) as well as the reference current input to theiMULT₃₀ are substantially desensitized to power supply variations, andwherein the voltage at the inputs of iMULT₃₀ substantially track powersupply voltage variations. The power supply desensitization mechanism isexplained as follows:

Bear in mind that FET early voltage (V_(A)) causes the FET's I_(DS) tovary with varying the FET's V_(DS). The V_(as) of the N4 y ₃₀ is about aV_(GS) of PyoM₃₀ below V_(DD), assuming low on resistance (low voltagedrop) across iDACx₃₀ current reference network current switches (N4 y′₃₀ and N4 y″ ₃₀) which causes the I_(DS) of the N4 y ₃₀ to vary. Thegate port of N4 y ₃₀ is coupled with a diode connected N4 r ₃₀ (whoseV_(DS) and V_(GS) are substantially equal). The I_(DS) of the N4 r ₃₀would vary with changes in V_(DD) since the V_(DS) of P4 r ₃₀ is aboutV_(DD) minus V_(GS) of N4 r ₃₀. The disclosed power supplydesensitization circuit (PSR₃₀) emulates a similar signal path from thegate port of P4 r ₃₀ to gate port of PyoM₃₀ (which is the output ofiDACx₃₀ and the input of iMULT₃₀). This is done for the current input ofiMULT₃₀ to be insensitive to power supply variations, while all iMULT₃₀,iDACx₃₀, iDACy₃₀, and RBN₃₀ current sources are without cascodes, whichsaves substantial silicon area.

This is how the PSR₃₀ circuit emulates a similar signal path from thegate port of P4 r ₃₀ to gate port of PyoM₃₀: The fixed current referenceIr′₃₀ is mirrored between Pc′₃₀ and Pc″₃₀ whose V_(DS) is V_(GS) of aPMOS and tracks each other with changes in V_(DD). The I_(DS) of diodeconnected Pc″₃₀ changes with V_(DD) variations in light of V_(DS) of theNc′₃₀ being V_(DD) minus V_(GS) of Pc″₃₀. The Nc′₃₀ and diode connectedNc₃₀ are mirrors, wherein V_(DS) of Pc₃₀ is V_(DD) minus the V_(GS) ofNc₃₀ which causes the I_(DS) of Nc₃₀ to change with V_(DD). Now, PcR₃₀substantially equalizes Ir′₃₀ with the I_(DS) of Pc′₃₀ by regulating thecurrent in Nc″₃₀ that is mirrored onto Nr′₃₀ which regulates the gatevoltage (and thus the I_(DS)) of Pr′₃₀ and Pc₃₀ as well as the gatevoltage (and thus the I_(DS)) of P4 r ₃₀, P2 r ₃₀, and P1 r ₃₀. Also,consider that I_(DS) of P4 r ₃₀, P2 r ₃₀, and P1 r ₃₀ (establishes thebus voltages V4 r ₃₀, V2 r ₃₀, and V1 r ₃₀) generate the sequence ofreference bias currents from the reference bias network (RBN₃₀).

In summary some of the benefits of the embodiment disclosed in FIG. 30are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the disclosed embodiment benefits from savings in silicon diearea, lower glitch, and faster speed when plurality of XD_(i)I_(O) arerequired (e.g., in machine learning applications where 1000s ofXD_(i)I_(O) may be needed) by utilizing the multiple iDAC method that isdisclosed in section 19.

Third, the disclosed embodiment benefits from further saving in silicondie area as well as desensitization to power supply variations for eachXD_(i)I_(O) by combining the multiple iDAC method with anotherembodiment of the multiplier power supply desensitization method, whichalso facilitates the elimination of the cascoded FETs in iDACs currentreference network as well as the PSR circuit.

Section 31—Description of FIG. 31

FIG. 31 is a circuit simulations showing the error waveform (outputcurrent SPICE simulation minus output current ideal) attributed to theoutput current (I_(o)) of a XD_(i)I_(O) that is arranged similar to thatof FIG. 30 but having an 8-bit digital inputs instead of 3-bits.

As noted, the XD_(i)I_(O) circuit whose simulation is provided in FIG.31 is inputted with an 8-bit (x-word digital input) by an 8-bit (y-worddigital input) wherein the x and y words are ramped the opposite of oneanother between zero-scale to full scale where power supply V_(DD) isvaried from 2V (the upper waveform of FIG. 31) to 1V (the lower waveformof FIG. 31).

FIG. 31 illustrates a waveform plot that is the error curve (i.e.XD_(i)I_(O)'s output current I_(O) simulation minus XD_(i)I_(O)'s outputcurrent I_(O) ideal) indicating under ±1% error in DNL (differentialnon-linearity), INL (integral non-linearity), and GE (gain-error) forV_(DD)=2v and V_(DD)=119, respectively. FIG. 31 indicates that theXD_(i)I_(O) with 8-bit digital inputs is substantially desensitized frompower supply variations by utilizing the multiplier power supplydesensitization method combined with the multiple iDAC method.

Section 32—Description of FIG. 32

FIG. 32 is a simplified block diagram illustrating a mesheddigital-to-analog multiplication (mD_(i)S_(o)) method. For clarity andnot as a limitation, the mD_(i)S_(o) method is described as receivingtwo digital words, each having 3-bits of resolution but the digitalinput word resolution can be higher (e.g., 16-bits). The digitalinput-bits are meshed with analog circuitry, wherein the digital bitscontrols are meshed with the reference network to perform bit-weightattribution and summation in the analog domain.

The mD_(i)S_(o) method of FIG. 32 is inputted with two digital inputwords that are x-bits wide (e.g., Dx₃₂ word with x=3) and y-bits wide(e.g., Dy₃₂ word with y=3). The mD_(i)S_(o) method is also inputted witha reference signal (Sr) that is scaled onto a bank of scaled referencenetworks (e.g., 1×Sr₃₂, 2×Sr₃₂, and 4×Sr₃₂). Plurality of y-channelsub-DACs (e.g., DAC1 y ₃₂, DAC2 y ₃₂, and DAC3 y ₃₂) each receiving theone respective bit of a y-digital input word (e.g., D1 y ₃₂, D2 y ₃₂,and D3 y ₃₂) control the steering (or transmission) of the scaledreference network to a plurality of x-channel sub-DAC's reference inputs(e.g., respective reference S_(R) inputs of DACx1 ₃₂, DACx2 ₃₂, andDACx3 ₃₂), wherein each x-channel sub-DAC receives the same x-digitalinput word (e.g., D Ix₃₂, D2 x ₃₂, and D3 x ₃₂). The outputs ofx-channel sub-DACs are combined to generate the final analogmultiplicand representation (Sxy₃₂) of the digital X·Y multiplications.Here, the analog output or S_(O) of DACx1 ₃₂, DACx2 ₃₂, and DACx3 ₃₂ arecombined together to generate Sxy₃₂. Note that for a binary (linear)multiplier, the scaled reference network is also binarily weighted, butthe reference network can be scaled in other fashions (e.g., equalweighted thermometer or non-linear or individually weighted, dependingon the transfer function requirement of the end-application).

In summary, the binary weighted version of the meshed digital-to-analogmultiplication method utilizes a multi-branch binary-weighted currentreference network, wherein each of the first binary weighted referencecurrent branches (y-branch) supply the current reference inputs of thesets of second binary weighted reference current branches (set ofx-branches). Accordingly, the digital X word or Dx₃₂ and the digital Yword or Dy₃₂ control the respective sets of analog switches that steer(or transmit) the combined respective x-branch analog signals to anoutput port (e.g., Sxy₃₂). Keep in mind that, the X and Y word bits andtheir respective X and Y DAC channels here are interchangeable give thecommutative property of multiplication. Benefits of utilizing the mesheddigital-to-analog multiplication method is discussed in the embodimentsof the said method, next.

Section 32′—Description of FIG. 32′

FIG. 32′ is another simplified block diagram illustrating the mesheddigital-to-analog multiplication (mD_(i)S_(O)) method. For clarity andnot as a limitation, the mD_(i)S_(O) method here is also described asreceiving two digital words, each having 3-bits of resolution but thedigital input word resolution can be higher as in for example 16-bits.The digital input-bits are also meshed with analog circuitry, whereinthey control a reference network that is arranged to perform bit-weightattribution and summation in the analog domain.

The mD_(i)S_(O) method of FIG. 32′ is inputted with two digital inputwords that are x-bits wide (e.g., Dx_(32′) word with x=3) and y-bitswide (e.g., Dy_(32′) word with y=3). Here, the mD_(i)S_(O) method isalso inputted with a reference signal (Sr) that is scaled onto threebanks of scaled reference networks (e.g., the y1-bank comprising of0.5×Sr_(32′), Sr_(32′), and 2Sr_(32′); the y2-bank comprising ofSr_(32′), 2Sr_(32′), and 4Sr_(32′); and the y3-bank comprising of2Sr_(32′), 4Sr_(32′), and 8Sr_(32′)).

Plurality of y-channel sub-DACs (e.g., DAC1 y _(32′), DAC2 y _(32′), andDAC3 y _(32′)) each receiving the one respective bit of a y-digitalinput word (e.g., D1 y _(32′), D2 y _(32′), and D³y_(32′)).

A clarification point regarding the FIG. 32′ illustration: In sub-DAC3 y_(32′), the digital bit D3 y _(32′) controls the 3 y-switches ofsub-DAC3 y _(32′) whose inputs receive a sequence of scaled referencesignals 8Sr_(32′), 4Sr_(32′), and 4Sr_(32′), wherein the 3 outputs ofthe sub-DAC3 y _(32′) are coupled to the 3 inputs of 3 x-switches ofsub-DACx3 _(32′) wherein the x-switches of sub-DACx3 _(32′) arecontrolled by the digital x-word (e.g., D1 x _(32′) to D3 x _(32′)bits). Also, in sub-DAC2 y _(32′), the digital bit D2 y _(32′) controlsthe 3 y-switches of sub-DAC2 y _(32′) whose inputs receive a sequence ofscaled reference signals 4Sr_(32′), 2Sr_(32′), and 1Sr_(32′), whereinthe 3 outputs of the sub-DAC2 y _(32′) are coupled to the 3 inputs of 3x-switches of sub-DACx2 _(32′) wherein the x-switches of sub-DACx2_(32′) are controlled by the digital x-word (e.g., D1 x _(32′) to D3 x_(32′) bits). Lastly, in sub-DAC1 y _(32′), the digital bit D1 y _(32′)controls the 3 y-switches of sub-DAC1 y _(32′) whose inputs receive asequence of scaled reference signals 2Sr_(32′), 1Sr_(32′), and0.5Sr_(32′), wherein the 3 outputs of the sub-DAC1 y _(32′) are coupledto the 3 inputs of 3 x-switches of sub-DACx1 _(32′) wherein thex-switches of sub-DACx1 _(32′) are controlled by the digital x-word(e.g., D1 x _(32′) to D3 x _(32′) bits).

The D1 y _(32′) bit steers the three reference sources 0.5×Sr_(32′),Sr_(32′), and 2Sr_(32′) onto the three switches of DACx1 _(32′) whichare controlled by D1 x _(32′), D2 x _(32′), and D3 x _(32′),respectively. The D2 y _(32′) bit steers the three reference sourcesSr_(32′), 2Sr_(32′), and 4Sr_(32′) onto the three switches of DACx2_(32′) which are controlled by D1 x _(32′), D2 x _(32′), and D3 x_(32′), respectively. And, the D3 y _(32′) bit steers the threereference sources 2Sr_(32′), 4Sr_(32′), and 8Sr_(32′) onto the threeswitches of DACx3 _(32′) which are controlled by D1 x _(32′), D2 x_(32′), and D3 x _(32′), respectively.

The outputs of x-channel sub-DACs (e.g., DACx1 _(32′), DACx2 _(32′), andDACx3 _(32′)) are combined to generate the final analog multiplicandrepresentation (Sxy_(32′)) of the digital X·Y multiplications. Here, theanalog output or S_(O) of DACx1 _(32′), DACx2 _(32′), and DACx3 _(32′)are added together to generate Sxy_(32′). Note that for a binary(linear) multiplier, the (three) banks of scaled reference network isalso binarily weighted, but the reference network can be scaled in otherfashions (e.g., thermometer or non-linear).

In summary, the binary weighted version of the meshed digital-to-analogmultiplication method utilizes banks of multi-branch binary-weightedcurrent reference network, wherein each of the Y-banks of the binaryweighted reference current branches (y-branch) supply the currentreference inputs of the sets of X-banks of the binary weighted referencecurrent branches (set of x-branches). Accordingly, the digital X word orDx_(32′) and the digital Y word or Dy_(32′) control the respective setsof analog switches that steer (or transmit) the combined respectivex-branch analog signals to an output port (e.g., Sxy_(32′)). Keep inmind that, the X and Y word bits and their respective X and Y DACchannels here are interchangeable given the commutative property ofmultiplication. Benefits of utilizing the meshed digital-to-analogmultiplication method is discussed in the embodiments of the saidmethod, next.

Section 33—Description of FIG. 33

FIG. 33 is a simplified circuit schematic illustrating a digital-inputto analog current output multiplier (XD_(i)I_(O)) as a preferredembodiment of the meshed digital-to-analog multiplication (mD_(i)S_(O))method described in the prior section 32′ and illustrated in FIG. 32′.Similarly, for clarity and not as a limitation, the XD_(i)I_(O)multiplier is described as receiving two digital words, each having3-bits of resolution wherein the digital input word resolution can be ashigh as 16-bits.

The XD_(i)I_(O) multiplier of FIG. 33 is inputted with two digital inputwords Dx₃₃ word (comprising of 3-bits D1 x ₃₃, D2 x ₃₃, and D3 x ₃₃) andDy₃₃ word (comprising of 3-bits D1 y ₃₃, D2 y ₃₃, and D3 y ₃₃).

The XD_(i)I_(O) multiplier here is also inputted with a referencecurrent signal (Ir) that is scaled onto a scaled reference network,comprising of 3 banks namely: First scaled reference current bank I1 r₃₃=1×I_(r), I2 r ₃₃=2×I_(r), and I4 r ₃₃=4×I_(r). Second scaledreference current bank I2 r′ ₃₃=2×I_(r), 14 r′ ₃₃=4×I_(r), and I8 r′₃₃=8×I_(r). Third scaled reference current bank I4 r″ ₃₃=4×I_(r), I8 r″₃₃=8×I_(r), and I16 r″ ₃₃=16×I_(r).

A first y-channel sub-iDAC receives the first scaled reference bank(i.e., I1 r ₃₃, I2 r ₃₃, and I4 r ₃₃) at its current switch inputs thatare the source-nodes of N1 y ₃₃, N1 y′ ₃₃, and N1 y″ ₃₃ whose gate-nodesare controlled by D1 y ₃₃ bit. Accordingly, I1 r ₃₃, I2 r ₃₃, and I4 r₃₃ currents are respectively steered through, N1 y ₃₃, N1 y′ ₃₃, and N1y″ ₃₃ which are gated by the D1 y ₃₃ bit, to provide the first x-channelsub-iDAC's reference input currents (in accordance with Dy₃₃ word).Consequently, the said first x-channel sub-iDAC reference currents aresteered through current switches N1 x ₃₃, N2 x ₃₃, and N3 x ₃₃ that arecontrolled by the first x-channel DAC's digital inputs D1 x ₃₃, D2 x ₃₃,and D3 x ₃₃. The drain-node currents of N1 x ₃₃, N2 x ₃₃, and N3 x ₃₃are summed together and coupled to Ixy₃₃, which is the analog currentoutput port of XD_(i)I_(O) multiplier.

Similarly, a second y-channel sub-iDAC receives the second scaledreference bank (i.e., I2 r′ ₃₃, 14 r′ ₃₃, and 18 r′ ₃₃) at its currentswitch inputs that are the source-nodes of N2 y ₃₃, N2 y′ ₃₃, and N2 y″₃₃ whose gate-nodes are controlled by D2 y ₃₃ bit. Accordingly, I2 r′₃₃, 14 r′ ₃₃, and 18 r′ ₃₃ currents are respectively steered through N2y ₃₃, N2 y′ ₃₃, and N2 y″ ₃₃ which are gated by the D2 y ₃₃ bit, toprovide the second x-channel sub-iDAC's reference input currents (inaccordance with Dy₃₃ word). Consequently, the said second x-channelsub-iDAC reference currents are steered through current switches N1 x′₃₃, N2 x′ ₃₃, and N3 x′ ₃₃ that are controlled by the second x-channelsub-DAC's same digital inputs D1 x ₃₃, D2 x ₃₃, and D3 x ₃₃. Thedrain-node currents of N1 x′ ₃₃, N2 x′ ₃₃, and N3 x′ ₃₃ are summedtogether and also coupled to Ixy₃₃.

Also, a third y-channel sub-iDAC receives the second scaled referencebank (i.e., I4 r″ ₃₃, 18 r″ ₃₃, and I16 r″ ₃₃) at its current switchinputs that are the source-nodes of N3 y ₃₃, N3 y′ ₃₃, and N3 y″ ₃₃whose gate-nodes are controlled by D3 y ₃₃ bit. Accordingly, I4 r″ ₃₃,I8 r″ ₃₃, and I16 r″ ₃₃ currents are respectively steered through, N3 y₃₃, N3 y′ ₃₃, and N3 y″ ₃₃ which are gated by the D3 y ₃₃ bit, toprovide the third x-channel sub-iDAC's reference input currents (inaccordance with Dy₃₃ word). Consequently, the said third x-channelsub-iDAC reference currents are steered through current switches N1 x″₃₃, N2 x″ ₃₃, and N3 x″ ₃₃ that are controlled by the third x-channelsub-DAC's same digital inputs D1 x ₃₃, D2 x ₃₃, and D3 x ₃₃. Thedrain-node currents of Nix′₃₃, N2 x′ ₃₃, and N3 x′ ₃₃ are summedtogether and also coupled to Ixy₃₃.

As noted above, the outputs of the first and second and third x-channeliDACs are summed at Ixy₃₃ to generate the analog multiplicandrepresentation of X·Y digital multiplications. Note that for a binary(linear) multiplier, the scaled reference network (bank) is alsobinarily weighted, but the reference network can be scaled in otherfashions (e.g., thermometer or non-linear).

In summary some of the benefits of the embodiment disclosed in FIG. 33are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the dynamic response of XD_(i)I_(O) multiplier is fast also inpart because the scaled reference network banks are constant currentsources whose current are steered by single MOFET switches which areinherently fast.

Third, current mirror loop associated with conventional multiplyingiDACs (where a first iDAC's output signal supplies the reference signalto a second iDAC, generally through a current mirror) is avoided whichhelps the speed.

Fourth, the minimum power supply can be very low since it is onlylimited by the drain-to-source voltage of current sources of the scaledreference network.

Section 34—Description of FIG. 34

FIG. 34 is a simplified circuit schematic illustrating another preferredembodiment of a digital-input to analog current output multiplier(XD_(i)I_(O)) that utilizes the meshed digital-to-analog multiplication(mD_(i)S_(O)) method described in section 32 and section 32′, andillustrated in FIG. 32 and FIG. 32′, respectively. Similarly, forclarity and not as a limitation, the XD_(i)I_(O) multiplier is describedas receiving two digital words, each having 3-bits of resolution whereinthe digital input word resolution can be as high as 16-bits.

The XD_(i)I_(O) multiplier of FIG. 34 is inputted with two digital inputwords Dx₃₄ word (comprising of 3-bits x1 ₃₄, x2 ₃₄, and x3 ₃₄) and Dy₃₄word (comprising of 3-bits y1 ₃₄, y2 ₃₄, and y3 ₃₄).

The XD_(i)I_(O) multiplier here is also inputted with a referencecurrent signal (i_(r)=1r₃₄) that is mirrored and scaled (via Ny₃₄) ontoa scaled reference network, comprising of 3 current sources: Firstscaled reference currents wherein the current through N1 y ₃₄=1×i_(r)that is split according to a programmed weight scale between N1 x ₃₄(e.g., scaled at 1×), N2 x ₃₄ (e.g., scaled at 2×), and N3 x ₃₄ (e.g.,scaled at 4×). Second scaled reference currents wherein the currentthrough N2 y ₃₄=2×i_(r) that is split according to a programmed weightscale between Nix′₃₄ (e.g., scaled at 1×), N2 x′ ₃₄ (e.g., scaled at2×), and N3 x′ ₃₄ (e.g., scaled at 4×). Third scaled reference currentswherein the current through N3 y ₃₄=4×i_(r) that is split according to aprogrammed weight scale between N1 x″ ₃₄ (e.g., scaled at 1×), N2 x″ ₃₄(e.g., scaled at 2×), and N3 x″ ₃₄ (e.g., scaled at 4×).

A first y-channel sub-iDAC receives the first scaled reference currents(i.e., I_(D) of N1 x ₃₄, N2 x ₃₄, and N3 x ₃₄) at its FET switch inputs(i.e., at source-nodes of coupled pairs M1 y ₃₄−M′1 y ₃₄, M1 y ₃₄−M′1 y₃₄, and M1 y ₃₄−M′1 y ₃₄) whose gate-nodes are controlled by the y1 ₃₄bit. Accordingly, the first y-channel sub-iDAC scaled referencecurrents, gated by the y1 ₃₄ bit, are outputted through the FETsswitches (i.e., as I_(D) of M1 y ₃₄, M1 y′ ₃₄, and M1 y″ ₃₄), whichprovide the first x-channel sub-iDAC reference currents. Consequently,the said first x-channel sub-iDAC reference currents are steered throughits FET current switches (i.e., at source-nodes of coupled pairs M1 x₃₄-M′1 x ₃₄, M2 x ₃₄-M′2 x ₃₄, and M3 x ₃₄-M′3 x ₃₄) that are controlledby the first x-channel sub-DAC's digital inputs x1 ₃₄, x2 ₃₄, and x3 ₃₄.The drain-node currents of M1 x ₃₄, M2 x ₃₄, and M3 x ₃₄ are summedtogether and coupled to Ixy₃₄, which is the analog current output portof XD_(i)I_(O) multiplier. Also, notice that drain-nodes of M′1 y ₃₄,M′1 y′ ₃₄, and M′1 y″ ₃₄ are coupled together and terminated at avoltage source (V1 ₃₄). Similarly, drain-nodes of M′1 x ₃₄, M′2 x ₃₄,and M′3 x ₃₄ are coupled together and terminated at a voltage source (V1₃₄).

Similarly, a second y-channel sub-iDAC receives the second scaledreference currents (i.e., I_(D) of N1 x′ ₃₄, N2 x′ ₃₄, and N3 x′ ₃₄) atits FET switch inputs (i.e., at source-nodes of coupled pairs M2 y₃₄-M′2 y ₃₄, M2 y ₃₄-M′2 y ₃₄, and M2 y ₃₄-M′2 y ₃₄) whose gate-nodesare controlled by the y2 ₃₄ bit. Accordingly, the second y-channelsub-iDAC scaled reference currents, gated by the y2 ₃₄ bit, areoutputted through the FETs switches (i.e., as I_(D) of M2 y ₃₄, M2 y′₃₄, and M2 y″ ₃₄), which provide the second x-channel sub-iDAC referencecurrents. Consequently, the said second x-channel sub-iDAC referencecurrents are steered through its FET current switches (i.e., atsource-nodes of coupled pairs M1 x′ ₃₄-M′1 x′ ₃₄, M2 x′ ₃₄-M′2 x′ ₃₄,and M3 x′ ₃₄-M′3 x′ ₃₄) that are controlled by the second x-channelsub-DAC's digital inputs x1 ₃₄, x2 ₃₄, and x3 ₃₄. The drain-nodecurrents of M1 x′ ₃₄, M2 x′ ₃₄, and M3 x′ ₃₄ are summed together andcoupled to Ixy₃₄ as well. Also, notice that drain-nodes of M′2 y ₃₄, M′2y′ ₃₄, and M′2 y″ ₃₄ are coupled together and also terminated at V1 ₃₄.Similarly, drain-nodes of M′1 x′ ₃₄, M′2 x′ ₃₄, and M′3 x′ ₃₄ arecoupled together and also terminated at V1 ₃₄.

Also, a third y-channel sub-iDAC receives the third scaled referencecurrents (i.e., I_(D) of N1 x″ ₃₄, N2 x″ ₃₄, and N3 x″ ₃₄) at its FETswitch inputs (i.e., at source-nodes of coupled pairs M3 y ₃₄-M′3 y ₃₄,M3 y ₃₄-M′3 y ₃₄, and M3 y ₃₄-M′3 y ₃₄) whose gate-nodes are controlledby the y3 ₃₄ bit. Accordingly, the third y-channel sub-iDAC scaledreference currents, gated by the y3 ₃₄ bit, are outputted through theFETs switches (i.e., as I_(D) of M3 y ₃₄, M3 y′ ₃₄, and M3 y″ ₃₄), whichprovide the third x-channel sub-iDAC reference currents. Consequently,the said third x-channel sub-iDAC reference currents are steered throughits FET current switches (i.e., at source-nodes of coupled pairs M1 x″₃₄-M′1 x″ ₃₄, M2 x″ ₃₄-M′2 x″ ₃₄, and M3 x″ ₃₄-M′3 x″ ₃₄) that arecontrolled by the third x-channel sub-DAC's digital inputs x1 ₃₄, x2 ₃₄,and x3 ₃₄. The drain-node currents of M1 x″ ₃₄, M2 x″ ₃₄, and M3 x″ ₃₄are summed together and coupled to Ixy₃₄ as well. Also, notice thatdrain-nodes of M′3 y ₃₄, M′3 y′ ₃₄, and M′3 y″ ₃₄ are coupled togetherand also terminated at V1 ₃₄. Similarly, drain-nodes of M′1 x″ ₃₄, M′2x″ ₃₄, and M′3 x″ ₃₄ are coupled together and also terminated at V1 ₃₄.

As such the outputs of the three x-channel sub-iDACs is summed at Ixy₃₄to generate the analog multiplicand representation of X·Y digitalmultiplications. Note that for a binary (linear) multiplier, the scaledreference network (bank) is also binarily weighted, but the referencenetwork can be scaled in other fashions (e.g., thermometer ornon-linear).

Note that coupling the iDAC switches gates to voltage sources V2 ₃₄ andV3 ₃₄ reduces logic gates that would otherwise be needed to drive theiDAC switches and it also reduces iDAC glitch (and thereby lowers theXD_(i)I_(O) multiplier glitch).

In summary some of the benefits of the embodiment disclosed in FIG. 34are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the dynamic response of XD_(i)I_(O) multiplier is fast also inpart because the scaled reference network banks are constant currentsources whose current are steered by single MOFET switches which areinherently fast.

Third, current mirror loop associated with conventional multiplyingiDACs (where a first iDAC's output signal supplies the reference signalto a second iDAC, generally through a current mirror) is avoided whichhelps the speed.

Fourth, utilizing the floating iDAC method surrounding N3 y ₃₄, N2 y ₃₄,and N1 y ₃₄ reduces die area.

Fifth, biasing one side of the iDAC switches by voltage sources (V2 ₃₄and V3 ₃₄) saves area and lowers the XD_(i)I_(O) multiplier glitch.

Section 35—Description of FIG. 35

FIG. 35 is a simplified circuit schematic illustrating another preferredembodiment of a digital-input to analog current output multiplier(XD_(i)I_(O)) that utilizes the meshed digital-to-analog multiplication(mD_(i)S_(O)) method described in section 32. In the embodiment of FIG.35, two digital words are inputted into a set of AND gates whose outputs(via current switches) control the steering of currents of a currentreference network, wherein the current reference network is arranged toperforms bit-weight attribution and summation in the analog domain (andin current mode).

FIG. 35 utilizes a x×y matrix of AND gates that are inputted with twodigital input words that are x-bits wide (Dx₃₅ word) and y-bits wide(Dy₃₅ word). The outputs of AND gates generate one digital output wordthat is x×y-bits wide (Dxy₃₅ word), wherein each bit of x×y-bits wideword has a respective weight. In FIG. 35's multi-branch binary-weightedcurrent reference network, each of the first binary weighted referencecurrent branches (x-branch) supply the current reference inputs of thesets of second binary weighted reference current branches (set ofy-branches). Accordingly, the Dxy₃₅ bits control the respective sets ofanalog current switches that steer the respective y-branch currents toeither a positive (I1 o ₃₅) or a negative (I2 o ₃₅) output currentports. Here, I1 o ₃₅ and I2 o ₃₅ represent the analog current outputs ofa digital input to analog current output multiplier (XD_(i)I_(O) ₃₅ ).

Consider that for descriptive clarity the embodiment of XD_(i)I_(O) ₃₅is illustrated with only 3-bit (x-bits) by 3-bit (y-bits) digital inputwords, but the resolution can be higher (e.g., 3-bits to 12-bits).Moreover, the x and y-bits and their respective iDAC channels here areinterchangeable give the commutative property of multiplications.

A current reference (Ir′₃₅) is inputted and mirrored onto iDACx₃₅'sbinary weighed current reference network, which constitutes the firstbinary weighted reference current branches (x-branch). The iDACx₃₅current reference network is comprising of P4 x ₃₅ (scaled at 4×), P2 x₃₅ (scaled at 2×), and P1 x ₃₅ (scaled at 1×).

In the FIG. 35 embodiment of a digital-input to analog current outputmultiplier (XD_(i)I_(O)) that utilizes the meshed digital-to-analogmultiplication (mD_(i)S_(O)) method, the functions of Y-branch iDACs andY-branch iDACs are meshed. Effectively, the multiplication function isperformed by digitally decoding the digital X-word and digital Y-wordand feeding the digitally decoded results onto respective pairs of iDAC1x ₃₅ & iDAC1 y ₃₅, iDAC2 x ₃₅ & iDAC2 y ₃₅, and iDAC3 x ₃₅ & iDAC3 y ₃₅which are arranged in a meshed structure.

Here also, the floating iDAC method (described earlier in section 1) isutilized, whereby each of the iDAC1 x ₃₅, iDAC2 x ₃₅, and iDAC3 x ₃₅binary weighted reference current branches (via each of the respectivePMOSFETs: P1 x ₃₅, P1 x ₃₅, and P1 x ₃₅) feed a respective currentreference inputs of 3 floating y-branch iDACs, which are the next set ofthree binary weighted reference current branches (set of 3 y-branches:iDAC1 y ₃₅, iDAC2 y ₃₅, and iDAC3 y ₃₅).

First, the drain terminal of P1 x ₃₅ (scaled at 1×) is coupled with thereference current input port of a first floating iDAC1 y ₃₅ comprisingof P14 y ₃₅ (scaled at 4×), P12 y ₃₅ (scaled at 2×), and P11 y ₃₅(scaled at 1×).

Second, the drain terminal of P2 x ₃₅ (scaled at 2×) is coupled with thereference current input port of a second floating iDAC2 y ₃₅ comprisingof P24 y ₃₅ (scaled at 4×), P22 y ₃₅ (scaled at 2×), and P21 y ₃₅(scaled 1×)_(.)

Third, the drain terminal of P4 x ₃₅ (scaled at 4×) is coupled with thereference current input port of a third floating iDAC3 y ₃₅ comprisingof P44 y ₃₅ (scaled at 4×), P42 y ₃₅ (scaled at 2×), and P41 y ₃₅(scaled at 1×).

The x-channel digital inputs (Dx₃₅ word) are D3 x ₃₅ (MSB) through D1 x₃₅ (LSB). The y-channel digital inputs (Dy₃₅ word) are D3 y ₃₅ (MSB)through D1 y ₃₅ (LSB).

The digital decoding can be accomplished by an AND matrix (AND₃₅) thatis inputted with digital input words Dx₃₅ and Dy₃₅, whose output is a3×3 bits wide word (Dxy₃₅ word). As noted earlier, each bit of the Dxy₃₅word has a respective weight and as such the Dxy₃₅ digital word controlsthe respective current switches of iDAC1 y ₃₅ (comprising of P11′₃₅,P12′₃₅, and P13′₃₅), iDAC2 y ₃₅ (comprising of P21′₃₅, P22′₃₅, andP23′₃₅), and iDAC3 y ₃₅ (comprising of P31′₃₅, P32′₃₅, and P34′₃₅). Forexample, when D3 x ₃₅ is high, then the output of the AND gates U34 y ₃₅through U31 ₃₅ respond to D3 y ₃₅ through D1 y ₃₅ considering theirrespective weights. Accordingly, P4 x ₃₅ current (having its respectiveweight) flows onto P44 y ₃₅ through P41 y ₃₅, in response to D3 y ₃₅through D1 y ₃₅ states, wherein P44 y ₃₅ through P41 y ₃₅ have theirrespective weights.

In the illustrated embodiment, to reduce glitch and lower dynamiccurrent consumption and to save logic area, the inverters and the buslines (that would otherwise be needed for the opposite polarity of theDxy₃₅ word) are eliminated. To attain such benefits, the biasing voltageVs₃₅ is coupled with the gate terminals of current switches of iDAC1 y₃₅ (comprising of P11 ₃₅, P12 ₃₅, and P13 ₃₅), iDAC2 y ₃₅ (comprising ofP21 ₃₅, P22 ₃₅, and P23 ₃₅), and iDAC3 y ₃₅ (comprising of P31 ₃₅, P32₃₅, and P34 ₃₅). The current switches P11′₃₅ through P34′₃₅ (whoseoutputs are coupled with the I1 o ₃₅ port) and P11 ₃₅ through P34 ₃₅(whose outputs are coupled with the I2 o ₃₅ port) steer their respectivecurrents onto the I1 o ₃₅ and I2 o ₃₅ ports in accordance with theirdigital selection, controlled by Dxy₃₅.

Notice that the 4X binary weighted (scaled) reference current through P4x ₃₅ is passed on through (to the iDAC3 y ₃₅) depending on the sign ofD3 x ₃₅, which is the MSB of the X-word. The 2× binary weighted (scaled)reference current through P2 x ₃₅ is passed on through (to the iDAC2 y₃₅) depending on the sign of D2 x ₃₅, which is the middle-bit of theX-word. The 1X binary weighted (scaled) reference current through P1 x₃₅ is passed on through (to the iDAC1 y ₃₅) depending on the sign of D1x ₃₅, which is the LSB of the X-word.

The selected sums of (analog) current switch outputs of iDAC1 y ₃₅through iDAC3 y ₃₅ are steered through the XD_(i)I_(O) ₃₅ 'scurrent-output port(s) I1 o ₃₅ (and I2 o ₃₅) that generate the analogcurrent product Ax₃₅×Ay₃₅/Ar₃₅, wherein Ax₃₅ is the analog currentrepresentation of the digital word Dx₃₅, Ay₃₅ is the analog currentrepresentation of the digital word Dy₃₅, and Ar₃₅ is scaled relative toreference current signal Ir′₃₅.

Bear in mind that the gate terminals of P11 y ₃₅ through P44 y ₃₅ arecoupled with a bias voltage source Vr₃₅, which leaves enough V_(DS)headroom for P1 x ₃₅ through P4 x ₃₅. Moreover, P11 y ₃₅ through P44 y₃₅ also function as cascoded FETs which can help increase the outputimpedance of the (XD_(i)I_(O) ₃₅ and) iDAC's current reference networks.Also consider that instead of a binary weighted current referencenetwork for the iDACs, other thermometer, linear, or non-linearreference network can be programmed here for different objectivetransfer functions.

The disclosed XD_(i)I_(O) ₃₅ benefits from current mode operations,which has been discussed in this disclosure. Multiplying a 3x3 bitdigital words generates a 6-bit word that can then be inputted to a6-bit iDAC to generate a current output product. Digital multipliers areexpensive and power hungry when they operate at full speed due todynamic power consumption of logic gates whose numbers increaseexponentially in with the length of a digital multiplier's input word.The embodiment of XD_(i)I_(O) ₃₅ that utilizes the disclosed mD_(i)I_(O)method requires a larger size current reference network compared to thatof a conventional a 6-bit iDAC but it requires a substantially smallerdigital logic, which net-net has the benefit of yielding a smaller diesize.

Section 36—Description of FIG. 36

FIG. 36 is a simplified block diagram illustrating a first non-lineardigital-to-analog converter (NDAC) method. For clarity and not as alimitation, the NDAC method is described as one with a square transferfunction. Utilizing the first NDAC method, Most-Significant-Portion(MSP) signals and Least-Significant-Portion (LSP) signals are generatedutilizing both non-linear DACs and linear DACs. The transfer function ofa non-linear MSP DAC can be arranged to follow a square transferfunction or other profiles including but not limited to logarithmic,wherein the linear LSP DACs can be arranged as a linear straight-lineapproximation to fill the gaps in-between the non-linear MSP DAC'soutput segment.

The first NDAC method of FIG. 36 is inputted with a digital input word(D₃₆) comprising of a Most-Significant-Bit (MSB) bank word or Dm₃₆ thatis m-bits wide, and a Least-Significant-Bit (LSB) bank word or Dn₃₆ thatis n-bits wide, and wherein D₃₆ is m+n bits wide.

The first NDAC method of FIG. 36 is provided with a non-linear MSP DAC(DACQ₃₆) that is inputted with the Dm₃₆ word. Moreover, DACQ₃₆ isinputted with a reference signal RSQ₃₆. The reference network of DACQ₃₆is programmed to follow a non-linear transfer function such as a squarein this illustration.

Furthermore, the first NDAC method of FIG. 36 is provided with a linearLSP DAC (DAC1L₃₆) that is inputted with the Dn₃₆ word. The DAC1L₃₆ isinputted with a reference signal RL1 ₃₆, wherein the magnitude of RL1 ₃₆is proportional to that of RSQ₃₆. The reference network of DAC1L₃₆ isprogrammed to follow a linear transfer function such as binary.

Moreover, the first NDAC method of FIG. 36 is provided with anotherlinear LSP DAC (DAC2L₃₆) that is inputted with the multiplicand productof Dm₃₆×Dn₃₆ words. The DAC2L₃₆ is inputted with a reference signal RL2₃₆, wherein the magnitude of RL2 ₃₆ is also proportional to that ofRSQ₃₆. The reference network of DAC2L₃₆ is also programmed to follow alinear transfer function such as binary.

The linear outputs of DAC1L₃₆ and DAC2L₃₆ are combined together togenerate an output that serves as a straight line approximation to fillthe gaps in-between MSP segments of the output of the non-linear DACQ₃₆.Utilizing the first NDAC method, a non-linear output signal (CO₃₆) canbe generated which is an analog non-linear representation of D₃₆, as afunction of an analog reference signal (e.g., scaled RSQ₃₆ signal).

In summary, the first non-linear digital-to-analog converter (NDAC)method of FIG. 36 is provided with at least one non-linear MSP DAC whoseoutput is combined with at least on linear LSP DAC, wherein the outputof linear LSP DAC(s) fill the gap in-between the non-linear MSP DACoutput segments. Benefits of utilizing the NDAC method is laterdiscussed in the embodiments of the said method.

Section 36′—Description of FIG. 36′

FIG. 36′ is a simplified block diagram illustrating a second non-lineardigital-to-analog converter (NDAC) method, which utilizes the mesheddigital-to-analog multiplication (mD_(i)S_(O)) method that is discussedin section 32 and illustrated in FIG. 32. Utilization of the mD_(i)S_(O)method is one of the differences between the second non-linear NDACmethod and the first NDAC method disclosed in section 36 and the thirdNDAC method disclosed in section 37. For clarity and not as alimitation, the second NDAC method is also described as one with asquare transfer function. Utilizing the second NDAC method,Most-Significant-Portion (MSP) signals and Least-Significant-Portion(LSP) signals can be generated utilizing non-linear DACs, a mesheddigital-input analog-output multiplier, and a linear offset DACs. Thetransfer function of a non-linear MSP DAC can be arranged to follow asquare transfer function or other profiles including but not limited tologarithmic, wherein the linear offset DAC in concert with the mesheddigital-input analog-output multiplier can be arranged as a linearstraight-line approximation to fill the gaps in-between the non-linearMSP DAC's output segment.

The second NDAC method of FIG. 36′ is inputted with a digital input word(D_(36′)) comprising of a Most-Significant-Bit (MSB) bank word or Dm₃₆,that is m-bits wide, and a Least-Significant-Bit (LSB) bank word orDn_(36′) that is n-bits wide, and wherein D_(36′) is m+n bits wide.

The second NDAC method of FIG. 36′ is provided with a non-linear MSP DAC(DACQ_(36′)) that is inputted with the Dm_(36′) word. Moreover,DACQ_(36′) is inputted with a reference signal RSQ_(36′). The referencenetwork of DACQ_(36′) is programmed to follow a non-linear transferfunction such as a square in this illustration.

Furthermore, the second NDAC method of FIG. 36′ is provided with alinear offset LSP DAC (DAC1L_(36′)) that is inputted with the Dn_(36′)word. The DAC1L_(36′) is inputted with a reference offset signal RL1_(36′), wherein the magnitude of RL1 _(36′) signal is proportional tothat of RSQ_(36′) signal. The reference network of DAC1L_(36′) isprogrammed to follow a linear transfer function such as binary.

Moreover, the NDAC method of FIG. 36′ is provided with a mesheddigital-to-analog multiplier (XDiSo_(36′)), which utilizes the mesheddigital-to-analog multiplication method (mD_(i)S_(O)) disclosed insection 32. The XDiSo₃₆, is inputted with a reference signal (RL2_(36′)), wherein the magnitude of RL2 _(36′) signal is also proportionalto that of RSQ_(36′) signal. The reference network of DAC2L_(36′) isalso programmed to follow a linear transfer function such as binary.

The linear outputs of DAC1L_(36′) and XDiSo_(36′) are combined togetherto generate an output that serves as a straight line approximation tofill the gaps in-between MSP segments of the output of the non-linearDACQ_(36′). Utilizing the second NDAC method, a non-linear output signal(CO_(36′)) can be generated which is an analog non-linear representationof D_(36′), as a function of an analog reference signal (e.g., scaledRSQ_(36′) signal).

In summary, the non-linear digital-to-analog converter (NDAC) method ofFIG. 36′ is provided with at least one non-linear MSP DAC whose outputis combined with a meshed digital-to-analog multiplier and at least onlinear (offset) LSP DAC, wherein the combined outputs of the mesheddigital-to-analog multiplier, and the linear LSP DAC(s), fill the gapin-between the non-linear MSP DAC output segments. Benefits of utilizingthe NDAC method is later discussed in the embodiments of the saidmethod.

Section 37—Description of FIG. 37

FIG. 37 is a simplified block diagram illustrating a third non-lineardigital-to-analog converter (NDAC) method. For clarity and not as alimitation, the third NDAC method here is also described as one with asquare transfer function. Utilizing the third NDAC method,Most-Significant-Portion (MSP) signals generated by a non-linear MSP DACare combined with and Least-Significant-Portion (LSP) signals generatedby a pair of linear LSP DACs which are arranged in a multiplyingfashion. The non-linear MSP DACs can also be arranged to follow a square(or other) profile(s) including but not limited to logarithmic, whereinthe linear LSP DACs can also be arranged as a linear straight-lineapproximation to fill the gaps in-between the outputs of the non-linearMSP DAC segment.

The third NDAC method of FIG. 37 is inputted with a digital input word(D₃₇) comprising of a Most-Significant-Bit (MSB) bank word or Dm₃₇ thatis m-bits wide, and a Least-Significant-Bit (LSB) bank word or Dn₃₇ thatis n-bits wide, and wherein D₃₇ word is m+n bits wide.

The third NDAC method of FIG. 37 is provided with a non-linear MSP DAC(DACQ₃₇) that is inputted with the Dm₃₇ word. Moreover, DACQ₃₇ isinputted with a reference signal RSQ₃₇. The reference network of DACQ₃₇is programmed to follow a non-linear transfer function such as a squarein this illustration.

Furthermore, the third NDAC method of FIG. 37 is provided with a linearLSP DAC (DAC1L₃₇) that is inputted with the MSB bank word Dm₃₇. TheDAC1L₃₇ is also inputted with a reference signal RL1 ₃₇, wherein themagnitude of RL1 ₃₇ is also proportional to that of RSQ₃₇. The referencenetwork of DAC1L₃₇ is also programmed to follow a linear transferfunction such as binary.

Moreover, the third NDAC method of FIG. 37 is provided with anotherlinear LSB DAC (DAC2L₃₇) that is inputted with the LSB bank word orDn₃₆. The output of DAC1L₃₇ is combined with a reference signal (RL2 ₃₇)and the said combined resultant signal is supplied to the referenceinput port of DAC2L₃₇. Note that the magnitude of RL1 ₃₇ signal and RL1₃₇ signal are also proportional to RSQ₃₇ signal.

The output the linear DAC2L₃₇ serves as a straight-line approximation tofill the gaps in-between Most-Significant-Portion (MSP) output segmentsof the non-linear DACQ₃₆. Utilizing the third NDAC method, a non-linearoutput signal (CO₃₇) can be generated which is an analog non-linearrepresentation of D₃₇, as a function of an analog reference signal(e.g., scaled RSQ₃₇ signal).

In summary, the third non-linear digital-to-analog converter (NDAC)method of FIG. 37 is provided with at least one non-linear MPS DAC whoseoutput is combined with a pair of linear LSP multiplying DACs, whereinthe output of a first multiplying DAC is coupled with the refernceibputof a second multiplying DAC, and wherein the output of the secondmultiplying DAC fill the gap in-between the non-linear MSP DAC segments.Benefits of utilizing the third NDAC method is later discussed in theembodiments of the said method.

Section 38—Description of FIG. 38

FIG. 38 is a simplified circuit schematic illustrating an embodiment ofa non-linear digital-input to analog current output digital-to-analogconverter (iNDAC₃₈), which utilizes the NDAC method described in section37 and illustrated in FIG. 37, wherein the non-linear output profile ofiNDAC₃₈ is programmed to approximate a square transfer function.

For clarity of description and illustration, FIG. 38 illustrates only6-bit iDACs, but this illustration is not a limitation of the disclosurehere. Here, the digital input word (Di₃₈) is comprising of D6 ₃₈, D5 ₃₈,D4 ₃₈, D3 ₃₈, D2 ₃₈, and D1 ₃₈ bits. Depending on an applicationrequirement, the disclosed iDAC can, for example, have 16-bits ofresolution.

The non-linear Most-Significant-Portion (MSP) DAC (iDACQ₃₈) is anon-linear thermometer iDAC. The iDACQ₃₈ non-linear thermometerreference current network is comprised of I1 r ₃₈=i_(r), I1 r ₃₈=3i_(r),I1 r ₃₈=5i_(r), I1 r ₃₈=7i_(r), I1 r ₃₈=9i_(r), I1 r ₃₈=11i_(r), and I1r ₃₈=13i_(r), wherein i_(r) is a (unit) scaled reference signal. Byinputting the MSB bank word (D6 ₃₈, D5 ₃₈, and D4 ₃₈) to a 3-bit inputto 7-bit output digital encoder (ENC₃₈), a 7-bit digital word isgenerated. The 7-bit output word of ENC₃₈ control the current switchesP1 t ₃₈, P2 t ₃₈, P3 t ₃₈, P4 t ₃₈, P5 t ₃₈, P6 t ₃₈, and P7 t ₃₈, whoseinputs are couple to their respective non-linear current source segmentsof the non-linear thermometer reference current network. The currentswitches control the steering of the non-linear current source segments.The outputs of the current switches are coupled together at node iQ₃₈wherein a non-linear MSP current signal is generated that approximates asquare profile.

The first linear Least-Significant-Portion (LSP) iDAC (iDAC1L₃₈) is alinear binary weighted iDAC. The iDAC1L₃₈ binary weighted referencecurrent network is comprised of I9 r ₃₈=8i_(r), I10 r ₃₈=4i_(r), and I11r ₃₈=2i_(r). The MSB bank word (D6 ₃₈, D5 ₃₈, and D4 ₃₈) controls thecurrent switches P6 d ₃₈, P5 d ₃₈, and P4 d ₃₈ whose inputs are coupleto their respective binary-weighted current sources (e.g., I9 r₃₈=8i_(r), I10 r ₃₈=4i_(r), and I11 r ₃₈=2 i_(r)). The P6 d ₃₈, P5 d ₃₈,and P4 d ₃₈ current switches control the steering of the respectivebinary-weighted current sources. The outputs of P6 d ₃₈, P5 d ₃₈, and P4d ₃₈ current switches are coupled together at node i1L₃₈ wherein a firstlinear LSP current signal is generated.

An offset reference signal I8 r ₃₈=i_(t) is also coupled to the i1L₃₈node, which is then coupled to the reference current input port of thesecond linear LSP iDAC (iDAC2L₃₈).

The second linear LSP iDAC or iDAC2L₃₈ is also a linear binary weightediDAC. The iDAC2L₃₈ binary scaled reference current network is comprisedof PMOSFETs: Pf₃₈@ 1X, P1 d′ ₃₈@1X, P2 d′ ₃₈@2X, and P3 d′ ₃₈@4X. TheLSB bank word (D1 ₃₈, D2 ₃₈, and D3 ₃₈) controls the current switches P1d ₃₈, P2 d ₃₈, and P3 d ₃₈ whose inputs are couple to their respectivebinary-scaled current dividers (e.g., P1 d′ ₃₈@1X, P2 d′ ₃₈@ 2X, and P3d′ ₃₈@4X). The P1 d ₃₈, P2 d ₃₈, and P3 d ₃₈ current switches controlthe steering of the respective binary-scaled current divider of the(reference input current of iDAC2L₃₈) supplied through the i1L₃₈ node.The outputs of P1 d ₃₈, P2 d ₃₈, and P3 d ₃₈ current switches arecoupled together at node i2L₃₈ wherein a second linear LSP currentsignal is generated.

The i2L₃₈ node and node iQ₃₈ node are coupled together and coupled tothe output node of the iNDAC₃₈ which is iCO₃₈.

Note that the current signals at the i2L₃₈ port fills-in the gap betweenthe current signals at the A_(QM) port. As such, the signal at nodeiCO₃₈ follows an approximate profile that is squarely weighted, as afunction of the i_(r), and is responsive to the Di₃₈ word.

In summary some of the benefits of the embodiment disclosed in FIG. 38are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the dynamic response of the non-linear iDAC is fast also in partbecause the scaled reference network banks utilized in the non-linearMSP, first linear LSP, and second linear LSP iDACs are constant currentsources whose current are steered by single MOFET switches which areinherently fast.

Third, current mirror loop associated with conventional multiplyingiDACs (where a first linear LSP iDAC's output signal supplies thereference signal to a second linear LSP iDAC, generally through acurrent mirror) is avoided which helps the speed.

Fourth, utilizing the floating iDAC method surrounding the first linearLSP iDAC and second linear LSP iDAC reduces die area and cost.

Fifth, the iNDAC₃₈ enables making a fast and low-cost digital input tocurrent analog output multiplier using the quarter square method. Here,by subtracting the current outputs of two iNDAC₃₈ a multiplicand 4X·Ycan be generated, wherein the first iNDAC₃₈ receives the sum of twodigital words and generates (X+Y)² and the second iNDAC₃₈ receives thedifference of the same two digital words and generates (X−Y)².

Section 39—Description of FIG. 39

FIG. 39 is a simplified circuit schematic illustrating anotherembodiment of a non-linear digital-input to analog current outputdigital-to-analog converter (iNDAC₃₉), which utilizes the NDAC methoddescribed in section 36′ and illustrated in FIG. 36′, wherein thenon-linear output profile of iNDAC₃₉ is programmed to approximate asquare transfer function. To generate a liner LSP current signal, theembodiment of FIG. 39 also utilizes another embodiment of adigital-input to current analog-output multiplier (XDiIo₃₉) thatutilizes the meshed digital-to-analog multiplication (mD_(i)S_(O))method that is discussed in sections 32 and 32′, and illustrated inFIGS. 32 and 32′. Bear in mind that XDiSo₃₉ multiplier is similar to theXD_(i)I_(O) disclosed in section and illustrated in FIG. 35.

For clarity of description and illustration, FIG. 39 illustrates only6-bit iNDACs, but this illustration is not a limitation of thedisclosure here. Here, the digital input word (Di₃₉) is comprising of D6₃₉, D5 ₃₉, D4 ₃₉, D3 ₃₉, D2 ₃₉, and D1 ₃₉ bits. Depending on anapplication requirement, the disclosed iDAC can, for example, have16-bits of resolution.

The non-linear Most-Significant-Portion (MSP) DAC (iDACQ₃₉) is arrangedas a non-linear thermometer iDAC. The iDACQ₃₉ non-linear thermometerreference current network is comprised of PMOSFETs whose drain currentsare scaled as follows: P1 t ₃₉@i_(r), P1 t ₃₉@3ir, P1 t ₃₉@5ir, P1 t₃₉@7ir, P1 t ₃₉@9ir, P1 t ₃₉@11i_(r), and P1 t ₃₉@13i_(r), wherein i_(r)is a (unit) scaled reference signal programmed by Ir₃₉=1i_(r′). Byinputting the MSB bank word (D6 ₃₉, D5 ₃₉, and D4 ₃₉) to a 3-bit inputto 7-bit output digital encoder (ENC₃₉), a 7-bit digital word isgenerated. The 7-bit output word of ENC₃₉ control the PMOSFET currentswitches comprising of s1 t ₃₉, s2 t ₃₉, s3 t ₃₉, s4 t ₃₉, s5 t ₃₉, s6 t₃₉, and s7 t ₃₉, whose inputs are couple to their respective non-linearcurrent source segments of the respective non-linear thermometerreference current network. As such, the current switches control thesteering of the non-linear current source segments onto the outputs ofthe said current switches which are coupled together at the output nodeiQ₃₉.

The first linear offset Least-Significant-Portion (LSP) iDAC (iDAC1L₃₉)is a linear binary weighted iDAC. The iDAC1L₃₉ binary weighted referencecurrent network is comprised of PMOSFETs whose drain currents are scaledat: P1 f ₃₉@½i_(r), P2 f ₃₉@ i_(r) and P3 f ₃₉@ 2i_(r). The LSB bankword (D1 ₃₉, D2 ₃₉, and D3 ₃₉) controls the PMOSFET current switches P1f ₃₉, P2 f ₃₉, and P3 f ₃₉ whose inputs are couple to their respectivebinary-weighted PMOSFET current sources (e.g., P1 f ₃₉@ 0.5X, P2 f ₃₉@1X, and P3 f ₃₉@ 2X). The P1 f ₃₉, P2 f ₃₉, and P3 f ₃₉ current switchescontrol the steering of the respective binary-weighted current sources.The outputs of P1 f ₃₉, P2 f ₃₉, and P3 f ₃₉ current switches arecoupled together at node iQ₃₉.

To generate the linear LSP output signal, the iNDAC₃₉ also utilizes theXDiSo₃₉ meshed multiplier, which utilizes the mD_(i)S_(O) method.

Similar to the XD_(i)I_(O) disclosed in section 35 and illustrated inFIG. 35, here in how XDiIo₃₉ of FIG. 39 is arranged:

The D4 ₃₉ bit is AND gated (e.g., via U41 ₃₉, U42 ₃₉, and U43 ₃₉) withthe LSB bank word (D3 ₃₉, D2 ₃₉, D1 ₃₉) to generate the control signalsfor a first sub-iDAC switches (s1L₃₉, s2L₃₉, and s3L₃₉). The firstsub-iDAC switches steer the first bank of binary weighted currentreference signals (generated by the PMOSFET binary scaled currentreference sources: P1L₃₉@ 1X, P2L₃₉@ 2X, and P3L₃₉@ 4X), wherein thefull scale of the first sub-iDAC is 7i_(r). The output of the firstsub-iDAC switches are also coupled together at node iQ₃₉.

The D5 ₃₉ bit is also AND gated (e.g., via U51 ₃₉, U52 ₃₉, and U53 ₃₉)with the LSB bank word (D3 ₃₉, D2 ₃₉, D1 ₃₉) to generate the controlsignals for a second sub-iDAC switches (s1L′₃₉, s2L′₃₉, and s3L′₃₉). Thesecond sub-iDAC switches steer the second bank of binary weightedcurrent reference signals (generated by the PMOSFET binary scaledcurrent reference sources: P1L′₃₉@ 2X, P2L′₃₉@ 4X, and P3L′₃₉@ 8X),wherein the full scale of the second sub-iDAC is 14i_(r). The output ofthe second sub-iDAC switches are also coupled together at node iQ₃₉.

The D6 ₃₉ bit is also AND gated (e.g., via U61 ₃₉, U62 ₃₉, and U63 ₃₉)with the LSB bank word (D3 ₃₉, D2 ₃₉, D1 ₃₉) to generate the controlsignals for a third sub-iDAC switches (s1L″₃₉, s2L″₃₉, and s3L″₃₉). Thethird sub-iDAC switches that steer the third bank of binary weightedcurrent reference signals (generated by the PMOSFET binary scaledcurrent reference sources: P1L″₃₉@ 4X, P2L″₃₉@ 8X, and P3L″₃₉@ 16X),wherein the full scale of the second sub-iDAC is 28i_(r). The output ofthe third sub-iDAC switches are also coupled together at node iQ₃₉.

Notice that the current output signal of the XDiIo₃₉ combined with theoutput signal of at the linear offset iDAC1L₃₉ fills-in the gap betweensegments of the current signal of the iDACQ₃₉. As such, the signal atnode iQ₃₉ follows an approximate squarely weighted profile, that is afunction of the i_(r), and is responsive to the Di₃₉ word.

In summary some of the benefits of the iNDAC₃₉ embodiment disclosed inFIG. 39 are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the dynamic response of the non-linear iDAC is fast also in partbecause the scaled reference network banks utilized in the non-linearMSP and the linear LSP segments are constant current sources whosecurrent are steered by single MOFET switches which are inherently fast.

Third, current mirror loop associated with conventional multiplyingiDACs (where for example a first linear LSP iDAC's output feeds thereference input port of a second linear LSP iDAC, generally through acurrent mirror) is avoided which helps the speed.

Fourth, utilizing a meshed digital input to analog output multiplierXDiIo₃₉ is fast and can operate with low V_(DD).

Fifth, the iNDAC₃₉ enables making a fast and low-cost digital input tocurrent analog output multiplier using the quarter square method. Here,by subtracting the current outputs of two iNDAC₃₉ a multiplicand 4A·Bcan be generated, wherein the first iNDAC₃₉ receives the sum of twodigital words and generates (A+B)² and the second iNDAC₃₉ receives thedifference of the same two digital words and generates (A−B)².

Sixth, the disclosed iNDAC₃₉ power consumption is event driven in thatif there is not event (e.g., data polarity of zero), the iDACs andXDiIo₃₉ shut of their respective current sources and hence power down.

Section 40—Description of FIG. 40

FIG. 40 is a simplified circuit schematic illustrating anotherembodiment of the digital-input to analog current output multiplier(XD_(i)I_(O)). The XD_(i)I_(O) ₄₀ multiplier utilizes the mesheddigital-to-analog multiplication (mD_(i)S_(O)) method (described in theprior section 32′ and illustrated in FIG. 32′), the multiple-channeldata-converter method (disclosed in section 19 and illustrated in FIG.19), and a second power supply desensitization method (PSR) disclosedhere.

The XD_(i)I_(O) of FIG. 40 (XD_(i)I_(O) ₄₀ ) utilizes a reference biasnetwork circuit (RBN₄₀) which is an embodiment of the multiple-channeldata-converter method (disclosed in section 19 and illustrated in FIG.19), which can save silicon area and improve the dynamic performancesub-iDACs, and thereby improve performance and reduce die size of theXD_(i)I_(O) ₄₀ . For clarity only one channel of XD_(i)I_(O) isdescribed here, but a sea of XD_(i)I_(O)s can be biased from the samereference bias network to bias the sea of XD_(i)I_(O) multipliers.

The XD_(i)I_(O) ₄₀ multiplier also utilizes the second multiplier powersupply desensitization method in the PRS₄₀ circuit that cansubstantially desensitize XD_(i)I_(O) ₄₀ multiplier's output currentfrom power supply variations, while eliminating cascodes from currentsources utilized in the current reference networks in the XD_(i)I_(O) ₄₀multiplier (which saves more area).

Also, for clarity and not as a limitation, the XD_(i)I_(O) ₄₀ multiplieris described as receiving two digital words, each having 3-bits ofresolution, but the digital input word resolution can be as high as16-bits.

The three sections of XD_(i)I_(O) multiplier circuit, comprising ofRBN₄₀, PSR₄₀, and XD_(i)I_(O) ₄₀ multiplier, is briefly described here:

In FIG. 40, a RBN₄₀ generates a sequence of individual binary weightedreference bias currents as follows: P16 r ₄₀ operating at I16 r ₄₀ of(2⁵⁻¹)×i=16i_(r40); P8 r ₄₀ operating at I8 r ₄₀ of (2⁴⁻¹)×i=8i_(r40);P4 r ₄₀ operating at I4 r ₄₀ of (2³⁻¹)×i=4i_(r40); P2 r ₄₀ operating atI2 r ₄₀ of (2²⁻¹)×i=2i_(r40); and P1 r ₄₀ operating at I1 r ₄₀ of(2¹⁻¹)×i=1i_(r40). In the embodiment of FIG. 40, RBN₄₀ is comprised of asequence of CCVS which are implemented as a sequence of diode connectedNMOSFETs (N16 r ₄₀, N8 r ₄₀, N4 r ₄₀, N2 r ₄₀, and N1 r ₄₀) whose gateand drain ports are coupled together, wherein each NMOSFET is scaledwith a W/L=1X. Accordingly, the sequence of binary weighted referencebias currents I16 r ₄₀ to I1 r ₄₀ are inputted to the diode connectedNMOSFETs (CCVS) which generate a sequence of (gate-to-source) referencebias voltages from reference bias voltage bus V16 ₄₀ to reference biasvoltage bus V1 ₄₀ as follows: I_(D) of P16 r ₄₀=16i_(r40) is inputted tothe diode connected N16 r ₄₀ to generate a reference bias bus voltage ofV16 ₄₀; I_(D) of P8 r ₄₀=8i_(r40) is inputted to the diode connected N8r ₄₀ to generate a reference bias bus voltage of V8 ₄₀; I_(D) of P4 r₄₀=4i_(r40) is inputted to the diode connected N4 r ₄₀ to generate areference bias bus voltage of V4 ₄₀; I_(D) of P2 r ₄₀=2i_(r40) isinputted to the diode connected N2 r ₄₀ to generate a reference bias busvoltage of V2 ₄₀; and I_(D) of P1 r ₄₀=1i_(r40) is inputted to the diodeconnected N1 r ₄₀ to generate a reference bias bus voltage of V1 ₄₀.

The NMOSFET current sources of the XD_(i)I_(O) ₄₀ multiplier are biasedby coupling their gate-port to the respective (reference bias network)RBN₄₀'s voltage bus comprising of V16 ₄₀ to V1 ₄₀ as follows:

For the first sub-iDAC of the meshed XD_(i)I_(O) ₄₀ multiplier, the gateports of NMOSFET current sources N1 v ₄₀, N2 v ₄₀, and N4 v ₄₀ arecoupled with reference bias voltage buses of RBN₄₀ comprising of V1 ₄₀,V2 ₄₀, and V4 ₄₀, respectively. Accordingly, the drain currents (scaledreference current sources) of N1 v ₄₀, N2 v ₄₀, and N4 v ₄₀ operate at1i_(r40), 2i_(r40), and 4i_(r40), respectively.

For the second sub-iDAC of the meshed XD_(i)I_(O) ₄₀ multiplier, thegate ports of NMOSFET current sources N2 v′ ₄₀, N4 v′ ₄₀, and N8 v′ ₄₀are coupled with reference bias voltage buses of RBN₄₀ comprising of V2₄₀, V4 ₄₀, and V8 ₄₀, respectively. Accordingly, the drain currents(scaled reference current sources) of N2 v′ ₄₀, N4 v′ ₄₀, and N8 v′ ₄₀operate at 2i_(r40), 4i_(r40), and 8i_(r40), respectively.

For the third sub-iDAC of the meshed XD_(i)I_(O) ₄₀ multiplier, the gateports of NMOSFET current sources N4 v″ ₄₀, N8 v″ ₄₀, and N16 v″ ₄₀ arecoupled with reference bias voltage buses of RBN₄₀ comprising of V4 ₄₀,V8 ₄₀, and V16 ₄₀, respectively. Accordingly, the drain currents (scaledreference current sources) of N4 v″ ₄₀, N8 v″ ₄₀, and N16 v″ ₄₀ operateat 4i_(r40), 8i_(r40), and 16i_(r40) respectively.

As indicated earlier, the PSR₄₀ circuit utilizes a second PSR method. Inthe embodiment of PSR₄₀ illustrated in FIG. 40, results in substantialarea savings by eliminating the cascode from current sources in thesub-iDACx₄₀s of the XD_(i)I_(O) ₄₀ multiplier as well as from that ofthe RBN₄₀ circuits, while the output current of XD_(i)I_(O) ₄₀multiplier is substantially desensitized from V_(DD) variations. This isdone by regulating the reference bias currents of RBN₄₀ so that theoutputs of the sub-iDACx₄₀s of the XD_(i)I_(O) ₄₀ multiplier aresubstantially desensitized to power supply variations.

The second power supply desensitization (PSR) method utilized in thePSR₄₀ circuit is briefly explained as follows:

A central reference bias current network (RBN), free of cascodes,generates a reference bias voltage bus, wherein the reference biasvoltage bus is shared with a plurality of reference bias currentnetworks of a plurality of cascode-free data-converters. Tosubstantially desensitize the plurality of output currents of theplurality of cascode-free data-converters, a power supplydesensitization circuit tracks the power supply variations and varieseach reference bias currents of the central RBN. Utilization of thesecond PSR method PSR₄₀ is described next. in Bear in mind that FETearly voltage (V_(A)) causes the FET's I_(DS) to vary with varying theFET's V_(DS). Also, keep in mind that the output port of the XD_(i)I_(O)₄₀ multiplier could be coupled to an input of a current-modeanalog-to-digital converter (iADC), wherein the input port of the iADCcould be biased at a V_(GS) of a MOSFET below or above the V_(DD) orV_(SS), respectively (e.g., V_(DD)−Vgs_(PMOS)). As such, assuming littlevoltage drop across current switches of the sub-iDACs of the XD_(i)I_(O)₄₀ multiplier, the drain-terminals of the (digitally selected) scaledreference current sources of the XD_(i)I_(O) ₄₀ multiplier would bebiased at V_(DD)−Vgs_(PMOS) as well. Additionally, keep in mind that thedrain-to-source voltage (V_(DS)) of current sources of the RBN₄₀ (e.g.,P16 r ₄₀, P8 r ₄₀, P4 r ₄₀, P2 r ₄₀, and P1 r ₄₀) isV_(DS)=V_(DD)−Vgs_(NMOS). In order to substantially desensitize theoutput current of the XD_(i)I_(O) ₄₀ multiplier from V_(DD) variations,the PSR₄₀ is arranged to operates as follows: P3 d ₄₀ regulates theI_(D) of the diode-connected N2 d ₄₀ (i.e., Vgs_(NMOS)) whose current ismirrored onto N1 d ₄₀. The I_(D) of N1 d ₄₀ is coupled into the diodeconnected P2 d ₄₀ (i.e., Vgs_(PMOS)) whose I_(D) is mirrored onto P1 d₄₀. The I_(D) of P1 d ₄₀ is substantially equal to that of the scaledreference current or ir₄₀. Accordingly, as the V_(DD) is varied, thegate port of P3 d ₄₀ regulates the magnitude of the current sources ofthe RBN₄₀ so that the current sources of the RBN₄₀ track the scaledreference current or ir₄₀, which is substantially stable by design. Insummary, the disclosed arrangement could substantially desensitize theXD_(i)O_(O) ₄₀ multiplier from V_(DD) variations while all currentsources of the sub-iDACx₄₀s of the XD_(i)O_(O) ₄₀ multiplier and that ofthe RBN₄₀ current sources are without cascodes, which saves substantialsilicon area.

Next, the XD_(i)I_(O) ₄₀ multiplier is briefly described, keeping inmind that the embodiment of XD_(i)I_(O) ₄₀ multiplier is similar to theembodiment of the XD_(i)I_(O) multiplier of FIG. 33 which utilized themeshed digital-to-analog multiplication (mD_(i)S_(O)) method (describedin the prior section 32′ and illustrated in FIG. 32′). The XD_(i)O_(O)₄₀ multiplier is inputted with two digital input words Dx₄₀ word(comprising of 3-bits x1 ₄₀, x2 ₄₀, and x3 ₄₀) and Dy₄₀ word (comprisingof 3-bits y1 ₄₀, y2 ₄₀, and y3 ₄₀).

As described earlier, the XD_(i)I_(O) ₄₀ multiplier is also inputtedwith a plurality of scaled reference current signals proportional toir₄₀, utilize NMOSFETs that are each scaled with W/L of 1X) comprisingof 3 banks namely: The first scaled reference current bank I1 r₄₀=1×ir₄₀, I2 r ₄₀=1×ir₄₀, and I4 r ₄₀=4×ir₄₀, corresponding to I_(D) ofN1 v ₄₀, N2 v ₄₀, and N4 v ₄₀, respectively. The second scaled referencecurrent bank I2 r ₄₀=2×ir₄₀, I4 r ₄₀=4×ir₄₀, and I8 r ₄₀=8×ir₄₀,corresponding to I_(D) of N2 v′ ₄₀, N4 v′ ₄₀, and N8 v′ ₄₀,respectively. The third scaled reference current bank I4 r ₄₀=4×ir₄₀, I8r ₄₀=8×ir₄₀, and I16 r ₄₀=16×ir₄₀, corresponding to I_(D) of N4 v″ ₄₀,N8 v″ ₄₀, and N16 v″ ₄₀, respectively.

A first x-channel sub-iDAC receives the first scaled reference bank(i.e., I1 r ₄₀, I2 r ₄₀, and I4 r ₄₀) at its current switch inputs thatare the source-nodes of N1 x ₄₀, N1 x′ ₄₀, and N1 x″ ₄₀ whose gate-nodesare controlled by x1 ₄₀ bit. Accordingly, each of the I1 r ₄₀, I2 r ₄₀,and I4 r ₄₀ currents are respectively steered through, N1 x ₄₀, N1 x′₄₀, and N1 x″ ₄₀ which are gated by the x1 ₄₀ bit, to provide the scaledreference input currents to the first y-channel sub-iDAC (in accordancewith Dx₄₀ word). Consequently, the said first y-channel sub-iDACreference currents are steered through current switches N1 y ₄₀, N2 y₄₀, and N3 y ₄₀ that are controlled by the first y-channel sub-iDAC'sdigital inputs y1 ₄₀, y2 ₄₀, and y3 ₄₀ bits, respectively. Thedrain-node currents of N1 y ₄₀, N2 y ₄₀, and N3 y ₄₀ are summed togetherand coupled to Ixy₄₀, which is the analog current output port of theXD_(i)I_(O 40) multiplier.

Similarly, a second x-channel sub-iDAC receives the second scaledreference bank (i.e., I2 r ₄₀, I4 r ₄₀, and I8 r ₄₀) at its currentswitch inputs that are the source-nodes of N2 x ₄₀, N2 x′ ₄₀, and N2 x″₄₀ whose gate-nodes are controlled by x2 ₄₀ bit. Accordingly, each ofthe I2 r ₄₀, I4 r ₄₀, and I8 r ₄₀ currents are respectively steeredthrough, N2 x ₄₀, N2 x′ ₄₀, and N2 x″ ₄₀ which are gated by the x2 ₄₀bit, to provide the scaled reference input currents to the secondy-channel sub-iDAC (in accordance with Dx₄₀ word). Consequently, thesaid second y-channel sub-iDAC reference currents are steered throughcurrent switches N1 y′ ₄₀, N2 y′ ₄₀, and N3 y′ ₄₀ that are controlled bythe second y-channel sub-iDAC's digital inputs y1 ₄₀, y2 ₄₀, and y3 ₄₀bits, respectively. The drain-node currents of N1 y′ ₄₀, N2 y′ ₄₀, andN3 y′ ₄₀ are summed together and coupled to Ixy₄₀, which as notedearlier is the analog current output port of the XD_(i)I_(O) ₄₀multiplier.

Lastly, a third x-channel sub-iDAC receives the third scaled referencebank (i.e., I4 r ₄₀, I8 r ₄₀, and I16 r ₄₀) at its current switch inputsthat are the source-nodes of N3 x ₄₀, N3 x′ ₄₀, and N3 x″ ₄₀ whosegate-nodes are controlled by x3 ₄₀ bit. Accordingly, each of the I4 r₄₀, I8 r ₄₀, and I16 r ₄₀ currents are respectively steered through, N3x ₄₀, N3 x′ ₄₀, and N3 x″ ₄₀ which are gated by the x3 ₄₀ bit, toprovide the scaled reference input currents to the third y-channelsub-iDAC (in accordance with Dx₄₀ word). Consequently, the said thirdy-channel sub-iDAC reference currents are steered through currentswitches N1 y″ ₄₀, N2 y″ ₄₀, and N3 y″ ₄₀ that are controlled by thethird y-channel sub-iDAC's digital inputs y1 ₄₀, y2 ₄₀, and y3 ₄₀ bits,respectively. The drain-node currents of N1 y′″ ₄₀, N2 y″ ₄₀, and N3 y″₄₀ are summed together and coupled to Ixy₄₀, which as just noted is theanalog current output port of the XD_(i)I_(O) ₄₀ multiplier.

In summary, the outputs of the first and second and third y-channeliDACs are summed at Ixy₄₀ to generate the analog multiplicandrepresentation, proportion to a unit scaled reference current signal,that is the X·Y digital multiplications. Note that for a binary (linear)multiplier, the scaled reference network (bank) is also binarilyweighted, but the reference network can be scaled in other fashions(e.g., thermometer or non-linear) for multipliers with differentinput-to-output transfer functions.

In conclusion, some of the benefits of the XD_(i)I_(O) multiplierembodiment disclosed in FIG. 40 are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the dynamic response of XD_(i)I_(O) multiplier is fast also inpart because the scaled reference network banks are constant currentsources whose current are steered by single MOFET switches which areinherently fast.

Third, current mirror loop associated with conventional multiplyingiDACs (where a first iDAC's output signal supplies the reference signalto a second iDAC, generally through a current mirror) is avoided whichhelps the speed.

Fourth, the minimum power supply can be lowered since it is chieflylimited by the drain-to-source voltage of current sources of the scaledreference network.

Fifth, for multiple channels of XD_(i)I_(O) multiplier required in AI &ML applications, the disclosed embodiment enjoys substantial benefitsattributed to the multiple-channel data-converter method summarized insection 19. There is an area savings, in utilizing the multiple-channeldata-converter method, in part because the requirement for individuallyweighted current sources (e.g., binary weighted or non-linearlyweighted) is decoupled from requiring individually scaled currentsources. Here, utilization of RBN₄₀ to generate a common referencevoltage bus that is shared between plurality of sub-iDACs reduces thesize of sub-iDACs current reference (cells in the) reference network ofeach sub-iDACs which lowers cost. Moreover, it lowers the combinedassociated parasitic and stray capacitance associated with currentreference cells, which improves each of the sub-iDAC's dynamic response,lowers glitch, lowers digital injections into power supplies, andreduces the disclosed sub-iDAC's dynamic power consumption. The smallsize and improved performance on each sub-iDAC used in arranging eachXD_(i)I_(O) multipliers are thus enjoyed by the plurality of pluralityof such XD_(i)I_(O) multipliers.

Sixth, despite area savings attainable by the disclosed multiple-channeldata-converter method in the sub-iDACs and the XD_(i)I_(O) multipliers,the accuracy of individual the sub-iDACs and the XD_(i)I_(O) multipliersare not substantially deterred. All else substantially equal, thematching of MOSFETs that form a data-converter's reference currentnetwork dominate the accuracy of a current-mode data-converter. Thescaled MOSFETs in both the (central) reference bias network (RBN₄₀)match the 1X scaled MOSFETs in each of the sub-iDACs and the XD_(i)I_(O)multipliers because they are all arranged with the same (non-minimum W/Lsize) cell layout and same orientation.

Seventh, the disclosed sub-iDACs and the XD_(i)I_(O) multiplierssubstantially reduces the number of MOSFETs that for example form thesub-iDAC's binary weighted current source network, and as such the fewerMOSFETs can be placed closer to each other on a chip. Similarly orientedand physically closer MOSFETs, that form the current reference networkof the sub-iDACs and the XD_(i)I_(O) multipliers, generally match betterwhich in turn improves the accuracy of each of the sub-iDACs and theXD_(i)I_(O) multipliers and the matching between them in plurality ofthe sub-iDACs and the XD_(i)I_(O) multipliers in one chip.

Eight, in AI & ML applications the output current of plurality of theXD_(i)I_(O) multipliers could be coupled together and coupled to theinput of iADCs. Generally and all else substantially equal, the largerthe W/L size of a FET current source of the XD_(i)I_(O) multipliers, thelarger the capacitance of the XD_(i)I_(O) multiplier's output port andthe slower the of the XD_(i)I_(O) multipliers output node. Moreover, theXD_(i)I_(O) multiplier's output can capacitively load an iADC's inputport which can also reduce the speed of the iADC right at its inputport. As noted earlier, the multiple-channel data-converter method hereenables decoupling the weight of a current source from the scaling ofthe sizes of FETs utilizing in forming the data-converter's referencecurrent sources. By keeping each of the W/L sizes of the current sourceFETs the same at 1x and small for example (despite each of their binaryweighted currents), the out node capacitances of the XD_(i)I_(O)multipliers that feeds the input of the iADC can be kept small which canhelp speeds up the dynamic response of the iADC.

Ninth, there are no passive devices in the disclosed sub-iDACs and theXD_(i)I_(O) multipliers, and as such there is no need for resistors orcapacitors, which reduces manufacturing size and cost.

Tenth, the disclosed sub-iDACs and the XD_(i)I_(O) multipliers utilizesame type of MOSFET current sources and MOSFET switches which aresymmetric and matched. Such arrangement facilitates device parameters totrack each other over process-temperature-operation conditionsvariations. Accordingly, each of the data-coefficient, power supplycoefficient, and AC power supply rejection performance can be enhancedand matched between the plurality of data-converters.

Eleventh, the disclosed embodiment enjoys the benefits of a second powersupply desensitization (PSR) method, which helps eliminate a cascode FETfrom the scaled current reference sources which saves area and improvesthe dynamic response of the sub-iDAC and that of the meshed multiplier.

Twelfth, in an embodiment of the disclosed sub-iDACs and the XD_(i)I_(O)multipliers that utilizes the multiple-channel data-converter methodwherein the central RBN is trimmed or calibrated for accuracy, theaccuracy of each of the plurality of data-converters, sub-iDACs, and theXD_(i)I_(O) multipliers whose reference current network is biased fromthe same central RBN can be improved.

Thirteenth, in an embodiment of the sub-iDACs and the XD_(i)I_(O)multipliers that utilizes multiple-channel data-converter method whereinthe central RBN is desensitized from power supply variations (e.g., byutilizing the second power supply desensitization method or the secondPSR method disclosed in FIG. 40 and FIG. 41), the power supplyinsensitivity of each of the plurality of data-converters whosereference current network is biased from the same central RBN can beimproved.

Fourteenth, the disclosed embodiment enjoys the benefits of mesheddigital-to-analog multiplication (mD_(i)S_(O)) method summarized insections 32′ and 33.

Fifteenth, the benefits of the sub-iDACs and the XD_(i)I_(O) multipliersutilizing the multiple-channel data-converter method can be attained inother higher-order systems including but not limited tomultiply-accumulate (MAC), and artificial-neural-network (ANN) thatutilize the multiple-channel data-converter method.

Section 41—Description of FIG. 41

FIG. 41 is a simplified circuit schematic illustrating anotherembodiment of the digital-input to analog current output multiplier(XD_(i)I_(O)), which can be extended for applications requiringplurality of XD_(i)I_(O) multipliers by sharing a central reference biasnetwork (RBN) that bias the current reference network of each of theXD_(i)I_(O) multipliers. The XD_(i)I_(O) ₄₁ multiplier utilizes a pairof non-linear iDACs, namely iNDAC_(P41) and iNDAC_(Q41), which receive asum and a difference of two digital words (X and Y) wherein for exampleP′=X+Y and Q′=X−Y. The outputs of the iNDAC_(P41) and iNDAC_(Q41) arethen subtracted via SUB₄₁ circuit which generates a scaled multiplicandanalog current of the multiplication on digital P′ word and digital Q′words. Here, by subtracting the current outputs of iNDAC_(P41) andiNDAC_(Q41) a multiplicand 4X. Y can be generated, wherein the firstiNDAC_(P41) receives the sum of two digital words and generates (X+Y)²and the second iNDAC_(Q41) receives the difference of the same twodigital words and generates (X−Y)².

The XD_(i)I_(O) ₄₁ multiplier utilizes the following circuit and methodsdisclosed earlier: (a) A RBN₄₁ circuit that utilizes themultiple-channel data-converter method disclosed in section 19, (b) apair of iNDAC_(P41) and iNDAC_(Q41) that utilizes the second non-lineardigital-to-analog converter or the NDAC method disclosed in section 36′.Each of iNDAC_(P41) and iNDAC_(Q41) are generally identical andsimilarly configured as the embodiment depicted in FIG. 39, except itdoes not use AND gate decoding; (c) The linear multiplication sectionsof iNDAC_(P41) and iNDAC_(Q41) are similar to the embodiments of FIG. 40and FIG. 33, wherein the linear multiplication sections utilized themeshed digital-to-analog multiplication or mD_(i)S_(O) method summarizedin sections 32′, and (d) the PSR₄₁ circuit is substantially similar tothe second power desensitization circuit embodiment and method or PSRsummarized in section 40.

The RBN₄₁ circuit generates the following reference bias voltages (bus)on diode connected NMOSFETs for mostly the linear sub-iDACs ofiNDAC_(P41) and iNDAC_(Q41): V₁ via V_(GS) of N₁ whose I_(D) is set byP₁'s I_(D)=1i_(r); V₂ via V_(GS) of N₂ whose I_(D) is set by P₂'sI_(D)=2i_(r); V₄ via V_(GS) of N₄ whose I_(D) is set by P₄'sI_(D)=4i_(r); V₈ via V_(GS) of N₈ whose I_(D) is set by P₈'sI_(D)=8i_(r); V₁₆ via V_(GS) of N₁₆ whose I_(D) is set by P₁₆'sI_(D)=16i_(r); V₃₂ via V_(GS) of N₃₂ whose I_(D) is set by P₃₂'sI_(D)=32i_(r).

Additionally, the RBN₄₁ circuit generates the following reference biasvoltages (bus) on diode connected NMOSFETs for mostly the non-lineariDACs of iNDAC_(P41) and iNDAC_(Q41) (e.g., iDACs whose input-outputtransfer functions approximates a square profile): V₂₄ via V_(GS) of N₂₄whose I_(D) is set by P₂₄'s=24i_(r); V₄₀ via V_(GS) of N₄₀ whose I_(D)is set by P₄₀'s I_(D)=40i_(r); V₅₆ via V_(GS) of N₅₆ whose I_(D) is setby P₅₆'s I_(D)=56i_(r); V₇₂ via V_(GS) of N₇₂ whose I_(D) is set byP₇₂'s I_(D)=72i_(r); V₈₈ via V_(GS) of N₈₈ whose I_(D) is set by P₈₈'sI_(D)=88i_(r); V₁₀₄ via V_(GS) of N₁₀₄ whose I_(D) is set by P₁₀₄'sI_(D)=104i_(r).

Similar to the circuit in section 40 and illustrated in FIG. 40, also inthe PSR₄₁ circuit here, the gate port of Pd₄₁ (through the loopcomprised of Nd₁, Nd₂, Pd₂, and Pd₃ and i_(r1)) regulates the scaledcurrent reference sources (e.g., P₁ through P₁₀₄) in order for theoutput currents of iNDAC_(P41) and iNDAC_(Q41) to be substantiallydesensitized to V_(DD) variations.

The SUB₄₁ is a simple embodiment of a current mirror that can performthe subtraction of the outputs current signals of the iNDAC_(P41) andthe iNDAC_(Q41) and generate the analog multiplicand current signal of4I_(XY). Note that to arrange a MAC which requires the summation of aplurality of multiplication results, the output of plurality of pairs ofnon-linear multiplier's outputs (e.g., plurality of iNDAC_(P41) andiNDAC_(Q41)) can be coupled to the opposite side of the same currentmirror circuit. As such, the current mirror can perform the function ofsubtraction (needed for pairs of non-linear DACs to generate themultiplicand results) and the function of addition (needed in MAC) withone subtractor circuit and in one shot, which save area, helps speed,and improves accuracy.

Next, the different sections of iNDAC_(P41) circuit is described inaccordance with the partitioning of the second non-lineardigital-to-analog converter or the NDAC method disclosed in section 36′:

The first linear offset LSP iDAC section of iNDAC_(P41) is a linearbinary weighted iDAC whose current reference network is comprised of(NMOSFETs scaled with W/L of 1X) N_(1P), N_(2P), and N_(3P) whichoperate at I_(D) of 1i_(r), 2i_(r), and 4i_(r), respectively. Thecurrent switches N_(1Pf), N_(2P f), and N_(3P f) are controlled by theLeast-Significant-Bit (LSB) bank word (e.g., P′₁, P′₂, and P′₃ bits)which respectively steer the reference currents 1i_(r), 2i_(r), and4i_(r) to the output port of the iNDAC_(P41).

The linear multiplication section of iNDAC_(P41) utilizes the mesheddigital-to-analog multiplication or mD_(i)S_(O) method summarized insections 32′, which is described next:

As described earlier, the linear multiplication section that utilizesthe meshed multiplication in iNDAC_(P41) is also arranged with aplurality of scaled reference current signals proportional to ir₄₀ (thatutilize NMOSFETs that are each scaled with W/L of 1X) comprising of 3banks namely: The first scaled reference current bank is comprised ofI_(D)=2i, through N_(4P), I_(D)=4i_(r) through N_(5P), and I_(D)=8i_(r)through N_(6P). The second scaled reference current bank is comprised ofI_(D)=4i_(r) through N_(7P), I_(D)=8i_(r) through N_(8P), and I_(D)=816through N_(9P). The third scaled reference current bank is comprised ofI_(D)=8i_(r) through N_(10P), I_(D)=16i_(r) through N_(11P), andI_(D)=32i_(r) through N_(12P).

A first MSP sub-iDAC utilized in the meshed multiplication section ofiNDAC_(P41) receives the first scaled reference bank (i.e., 2i_(r),4i_(r), and 8i_(r)) at its current switch inputs that are thesource-nodes of N_(4p) and N_(4p′) and N_(4p″). These current switchesare controlled by P′₄ bit. Accordingly, each of 2i_(r), 4i_(r), and8i_(r) currents, which are gated by the P′₄ bit, are respectivelysteered through current switches N_(4p) and N_(4p′) and N_(4p″) toprovide the scaled reference input currents to the first LSP sub-iDAC.Next, the said first LSP sub-iDAC reference currents are steered throughcurrent switches N_(1p) and N_(2p) and N_(3p) that are controlled by thefirst LSP sub-iDAC's digital inputs P′₁, P′₂, and P′₃ bits,respectively. The output of current switches N_(1p) and N_(2p) andN_(3p) are summed together and coupled to the output port of theiNDAC_(P41).

Similarly, a second MSP sub-iDAC utilized in the meshed multiplicationsection of iNDAC_(P41) receives the second scaled reference bank (i.e.,4i_(r), 8i_(r), and 16i_(r)) at its current switch inputs that are thesource-nodes of N_(5p) and N_(5p′) and N_(5p″). These current switchesare controlled by P′₅ bit. Accordingly, each of 4i_(r), 8i_(r), and16i_(r) currents, which are gated by the P′₅ bit, are respectivelysteered through current switches N_(5p) and N_(5p′) and N_(5p″) toprovide the scaled reference input currents to the first LSP sub-iDAC.Next, the said first LSP sub-iDAC reference currents are steered throughcurrent switches N_(1p′) and N_(2p′) and N_(3p′) that are controlled bythe first LSP sub-iDAC's digital inputs P′₁, P′₂, and P′₃ bits,respectively. The output of current switches N_(1p′) and N_(2p′) andN_(3p′) are summed together and coupled to the output port of theiNDAC_(P41).

Furthermore, a third MSP sub-iDAC utilized in the meshed multiplicationsection of iNDAC_(P41) receives the second scaled reference bank (i.e.,8i_(r), 16i_(r), and 32i_(r)) at its current switch inputs that are thesource-nodes of N_(6p) and N_(6p′) and N_(6p″). These current switchesare controlled by P′₆ bit. Accordingly, each of 4i_(r), 8i_(r), and16i_(r) currents, which are gated by the P′₆ bit, are respectivelysteered through current switches N_(6p) and N_(6p′) and N_(6p″) toprovide the scaled reference input currents to the first LSP sub-iDAC.Next, the said first LSP sub-iDAC reference currents are steered throughcurrent switches N_(1p″) and N_(2p″) and N_(3p″) that are controlled bythe first LSP sub-iDAC's digital inputs P′₁, P′₂, and P′₃ bits,respectively. The output of current switches N_(1p″) and N_(2p″) andN_(3p″) are summed together and coupled to the output port of theiNDAC_(P41).

The non-linear MSP iDAC section of the iNDAC_(P41) is arranged as anon-linear (e.g., to approximate a square transfer function) thermometeriDAC. Here, the non-linear thermometer reference current network iscomprised of NMOSFETs that are scaled with W/L of 1x, namely N_(13P)through N_(19P). The gate-ports N_(13P) through N_(19P)) arerespectively coupled to the reference network voltage bus V₈, V₂₄, V₄₀,V₅₆, V₇₂, V₈₈, and V₁₀₄, which are supplied from RBN₄₁ circuit. Thedrain currents of N_(13P) through N_(19P) are scaled to 8i_(r), 24i_(r),40i_(r), 56i_(r), 72i_(r), 88i_(r), and 104i_(r) wherein i_(r) isprogrammed by Ir₁. By inputting the proper polarity of the MSB bank word(xP′₆, xP′₅, and xP′₄) to a 3-bit input to 7-bit output digital encoder(ENC_(P)), a 7-bit digital word is generated. The 7-bit output word ofENC_(P) control the NMOSFET current switches comprising of N_(t1p),N_(t2p), N_(t3p), N_(t4p), N_(t5p), N_(t6p), and N_(t7p) whose inputsare couple to their respective non-linear current source segments (e.g.,8i_(r), 24i_(r), 40i_(r), 56i_(r), 72i_(r), 88i_(r), and 104i_(r)) ofthe respective non-linear thermometer reference current network. Assuch, the current switches control the steering of the non-linearcurrent source segments onto the outputs of the said current switcheswhich are coupled together at the output node of the iNDAC_(P41).

The iNDAC_(Q41) is arranged and operates the same as iNDAC_(P41).

As noted earlier, an analog multiplicand current signal of 4X. Y can begenerated by (setting P′=X+Y and Q′=X−Y and) inputting the properpolarity of P′ and Q′ into the digital input ports of iNDAC_(P41) andiNDAC_(Q41), and then subtracting the outputs of iNDAC_(P41) andiNDAC_(Q41) via SUB₄₁. Bear in mind that as such, the iNDAC_(P41)receives the sum of two digital words and generates (X+Y)² and theiNDAC_(Q41) receives the difference of the same two digital words andgenerates (X−Y)² and the (X+Y)²−(X−Y)²=4XY.

In conclusion, some of the benefits of the XD_(i)I_(O) multiplierembodiment disclosed in FIG. 41 are as follows:

First, the disclosed embodiment benefits from operating in current modethat has been discussed in this disclosure

Second, the dynamic response of XD_(i)I_(O) multiplier is fast also inpart because the scaled reference network banks are constant currentsources whose current are steered by single MOFET switches which areinherently fast.

Third, current mirror loop associated with conventional multiplyingiDACs (where a first iDAC's output signal supplies the reference signalto a second iDAC, generally through a current mirror) is avoided whichreduces die size and helps improve dynamic response.

Fourth, the minimum power supply can be lowered since it is chieflylimited by the drain-to-source voltage of current sources of the scaledreference network.

Fifth, the disclosed embodiment of XD_(i)I_(O) ₄₁ multiplier enjoys thebenefits of the RBN₄₁ circuit that utilizes the multiple-channeldata-converter method disclosed in section 19.

Sixth, the disclosed embodiment of XD_(i)I_(O) ₄₁ multiplier enjoys thebenefits of the pair of iNDAC_(P41) and iNDAC_(Q41) that utilizes thesecond non-linear digital-to-analog converter method disclosed insection 36′.

Seventh, the disclosed embodiment of XD_(i)I_(O) ₄₁ multiplier enjoysthe benefits of iNDAC_(P41) and iNDAC_(Q41) which are similarlyconfigured to the embodiment disclosed in section 39.

Eight, the disclosed embodiment of XD_(i)I_(O) ₄₁ multiplier enjoys thebenefits of the linear multiplication sections of iNDAC_(P41) andiNDAC_(Q41) which are similar to the embodiments disclosed in sections40 and 33, wherein the linear multiplication sections utilized themeshed digital-to-analog multiplication method summarized in sections32′, and

Ninth, the disclosed embodiment of XD_(i)I_(O) ₄₁ multiplier enjoys thebenefits of the PSR₄₁ circuit that is substantially similar to thesecond power desensitization circuit embodiment and method summarized insection 40.

An inherent benefit of the disclosed embodiment of XD_(i)I_(O) ₄₁multiplier is that since both digital inputs to the XD_(i)I_(O) ₄₁multiplier (e.g., x+y and x−y) are squared and subsequently the (x+y)²term and the (x−y)² term are subtracted from one another, the 4xymultiplicand result can be bi-directional which is beneficial formulti-quadrant signal processing.

Section 42—Description of FIG. 42

FIG. 42 is a SPICE circuit simulations that illustrates the linearityerror in % between an ideal output current (Io_(ideal)) of a XD_(i)I_(O)versus the simulated output current (Io_(simulation)) of a XD_(i)I_(O)that is arranged similar to that of FIG. 34 but with a 4-bit resolution.

Keeping in mind that 4-bit of resolution computes to about 6% ofaccuracy, FIG. 42 indicates DNL (differential non-linearity) and INL(integral non-linearity) of less than about ±3%. The X and Y digitalinput words span in the opposite direction, between zero and full scale,while stepping the digital words with one LSB increments each 1micro-seconds (μs). The lower graph in FIG. 42 indicates a powerconsumption of less than about 80 nano-ampere.

Section 43—Description of FIG. 43

FIG. 43 is a SPICE circuit simulations that illustrates the linearityerror in % between an ideal output current Io_(ideal)) of a XD_(i)I_(O)versus the simulated output current (Io_(simulation)) of a XD_(i)I_(O)multiplier that is arranged similar to that of FIG. 40 but with a 6-bitresolution.

As noted, the XD_(i)I_(O) multiplier of FIG. 43 is inputted with an6-bit (X-word digital input) by an 6-bit (Y-word digital input) whereinthe X and Y digital input words are ramped in the same direction betweenzero-scale to full scale. Here, the linearity of XD_(i)I_(O) isillustrated for power supply V_(DD)=2V (in the lower waveform of FIG.43) and V_(DD)=2V (in the upper waveform of FIG. 43).

Keeping in mind that 6-bit of resolution computes to about 1.6% ofaccuracy, FIG. 43 indicates DNL (differential non-linearity), INL(integral non-linearity), and GE (gain-error) of less than about ±1.6%for V_(DD) between 1V to 2V. By utilizing the multiplier power supplydesensitization method combined with the multiple-channel iDAC method ina XD_(i)I_(O), FIG. 43 indicates that the XD_(i)I_(O) is substantiallydesensitized from power supply variations.

Section 44—Description of FIG. 44

FIG. 44 illustrates SPICE circuit simulations comprising of an idealsquare iDAC's output current (IX) plot versus the simulated outputcurrent (I_(O) ²) plot of a square iDAC that is arranged similar to thatof FIG. 38 but with a 7-bit resolution.

Keeping in mind that 7-bit of resolution computes to about 0.8% ofaccuracy, the lower graph in FIG. 44 indicates a % error between IX andto indicating less than about ±0.8% error in DNL (differentialnon-linearity) and INL (integral non-linearity). The X and Y digitalinput words span in the same direction, between full scale and zero. Theupper graph in FIG. 44 is a plot of the square iDAC's I° output currentsimulation versus that of an ideal square iDAC (offset by a few % forclarity of the illustration).

Section 45—Description of FIG. 45

FIG. 45 illustrates SPICE circuit simulations comprising of an idealsquare iDAC's output current (I_(X) ²) plot versus the simulated outputcurrent (I_(O) ²) plot of a square iDAC that is arranged similar to thatof FIG. 39 but with a 7-bit resolution.

Keeping in mind that 7-bit of resolution computes to about 0.8% ofaccuracy, the upper graph in FIG. 45 indicates a % error between I_(X) ²and I_(O) ² indicating less than about ±0.8% error in DNL (differentialnon-linearity) and INL (integral non-linearity). The X and Y digitalinput words span in the same direction, between zero and full scale. Thelower graph in FIG. 44 is a plot of the square iDAC's I_(o) outputcurrent simulation versus that of an ideal square iDAC (offset by a few% for clarity of the illustration).

Section 46—Description of FIG. 46

FIG. 46 illustrates SPICE circuit simulations comprising of an idealXD_(i)I_(O)'s output current (IO_(ideal)) plot versus the simulatedoutput current (Io_(simulation)) plot of a XD_(i)I_(O) multiplier thatis arranged similar to that of FIG. 41 but with a 7-bit resolution. As areminder the XD_(i)I_(O) multiplier utilizes iDACs whose transferfunctions follows an approximate square transfer function. Also, notethat Io_(ideal)=((x+y)²−(x−y)²)=4xy

As noted, the XD_(i)I_(O) multiplier of FIG. 41 is inputted with a 7-bit(X+Y) and a 7-bit (X−Y) digital words, wherein X and Y digital words areramped in the same direction between zero-scale to full scale.

Keeping in mind that 7-bit of resolution computes to about 0.8% ofaccuracy, FIG. 46 indicates DNL (differential non-linearity) and INL(integral non-linearity) of less than about ±0.8%.

What is claimed:
 1. A non-linear digital-to-analog conversion (NDAC)method in an integrated circuit, the method comprising: generating anon-linear Most-Significant-Portion (MSP) analog output signal (So_(MSP)^(N)) that is proportional to a MSP reference signal (Sr_(MSP)), and isresponsive to a bank of Most-Significant-Bits (MSBs) of a digital inputword (Di_(MSP)); generating a linear Least-Significant-Portion (LSP)analog output signal (So_(LSP) ^(L)) that is proportional to a LSPreference signal (Sr_(LSP)), and is responsive to a bank ofLeast-Significant-Bits (LSBs) of a digital word (Di_(LSP)), and isresponsive to the Di_(MSP) word; combining the So_(MPS) ^(N) signal andthe So_(LSP) ^(L) signal to generate a non-linear analog output signal(So_(N)) that is proportional to a reference signal (S_(R)), and isresponsive to a digital word (D_(I)), wherein the So_(LSP) ^(L) signalis a straight-line approximation between non-linear segments of the(So_(MSP) ^(N)) signal; wherein the Sr_(MSP) signal, and the Sr_(LSP)signal, are each proportional to the S_(R) signal; and wherein the D_(I)word is comprised of the Di_(MSP) word and the Di_(LSP) word; generatingthe So_(LSP) ^(L) signal by a plurality of linear LSP Digital-to-AnalogConverters (DAC_(LSP) ^(L))s comprised of a first linear LSP DAC (DAC1_(LSP) ^(L)), and a second linear LSP DAC (DAC2 _(LSP) ^(L)); generatingan output signal (So1 _(LSP) ^(L)) by the DAC1 _(LSP) ^(L) that isproportional to a first LSP reference signal (Sr1 _(LSP)), and isresponsive to the Di_(MSP) word; combining the So1 _(LSP) ^(L) signalwith a reference offset signal (Sr_(OFS)) to generate a second referencesignal (Sr2 _(LSP) ^(L)); receiving the Sr2 _(LSP) ^(L) signal into areference input port (Ar2 _(LSP) ^(L)) of the DAC2 _(LSP) ^(L); andgenerating the So_(LSP) ^(L) signal at an output port (Ao2 _(LSP) ^(L))of the DAC2 _(LSP) ^(L) that is responsive to the Di_(LSP) word and theDi_(MSP) word.
 2. A non-linear digital-to-analog conversion (NDAC)method in an integrated circuit, the method comprising: generating anon-linear Most-Significant-Portion (MSP) analog output signal (So_(MSP)^(N)) that is proportional to a MSP reference signal (Sr_(MSP)), and isresponsive to a bank of Most-Significant-Bits (MSBs) of a digital inputword (Di_(MSP)); generating a linear Least-Significant-Portion (LSP)analog output signal (So_(LSP) ^(L)) that is proportional to a LSPreference signal (Sr_(LSP)), and is responsive to a bank ofLeast-Significant-Bits (LSBs) of a digital word (Di_(LSP)), and isresponsive to the Di_(MSP) word; combining the So_(MPS) ^(N) signal andthe So_(LSP) ^(L) signal to generate a non-linear analog output signal(So_(N)) that is proportional to a reference signal (S_(R)), and isresponsive to a digital word (D_(I)); wherein the So_(LSP) ^(L) signalis a straight-line approximation between non-linear segments of the(So_(MSP) ^(N)) signal; wherein the Sr_(MSP) signal, and the Sr_(LSP)signal, are each proportional to the S_(R) signal; and wherein the D_(I)word is comprised of the Di_(MSP) word and the Di_(LSP) word;multiplying the Di_(LSP) word and the Di_(MSP) word to generate amultiplicand digital word (Di_(LSP)×Di_(MSP)); generating an outputsignal (So1 _(LSP) ^(L)) by a first LSP Digital-to-Analog Converter(DAC1 _(LSP) ^(L)), wherein the So1 _(LSP) ^(L) signal is proportionalto a first LSP reference signal (Sr1 _(LSP)), and is responsive to theDi_(LSP)×Di_(MSP) word; generating an output offset signal (Sfo_(LSP)^(L)) by a second LSP Digital-to-Analog-Converter (DAC2 _(LSP) ^(L)),wherein Sfo_(LSP) ^(L) signal is proportional to a second LSP referencesignal (Sr2 _(LSP)), and is responsive to the Di_(LSP) word; andcombining the So1 _(LSP) ^(L) signal and the Sfo_(LSP) ^(L) signal togenerate the So_(LSP) ^(L) signal.
 3. A non-linear digital-to-analogconversion (NDAC) method in an integrated circuit, the methodcomprising: generating a non-linear Most-Significant-Portion (MSP)analog output signal (So_(MSP) ^(N)) that is proportional to a MSPreference signal (Sr_(MSP)), and is responsive to a bank ofMost-Significant-Bits (MSBs) of a digital input word (Di_(MSP));generating a linear Least-Significant-Portion (LSP) analog output signal(So_(LSP) ^(L)) that is proportional to a LSP reference signal(Sr_(LSP)), and is responsive to a bank of Least-Significant-Bits (LSBs)of a digital word (Di_(LSP)), and is responsive to the Di_(MSP) word;combining the So_(MPS) ^(N) signal and the So_(LSP) ^(L) signal togenerate a non-linear analog output signal (So_(N)) that is proportionalto a reference signal (S_(R)), and is responsive to a digital word(D_(I)); wherein the So_(LSP) ^(L) signal is a straight-lineapproximation between non-linear segments of the (So_(MSP) ^(N)) signal;wherein the Sr_(MSP) signal, and the Sr_(LSP) signal, are eachproportional to the S_(R) signal; and wherein the D_(I) word iscomprised of the Di_(MSP) word and the Di_(LSP) word; receiving theDi_(LSP) word and the Di_(MSP) word into a linearly meshed digital-inputto analog-output multiplier (mDiSo_(LSP) ^(L)) to generate an outputsignal (So1 _(LSP) ^(L)) that is proportional to a first LSP referencesignal (Sr1 _(LSP)); generating an output offset signal (Sfo_(LSP) ^(L))by a second LSP Digital-to-Analog-Converter (DAC2 _(LSP) ^(L)) that isproportional to a second LSP reference signal (Sr2 _(LSP)), and isresponsive to the Di_(LSP) word; and combining So1 _(LSP) ^(L) signaland the Sfo_(LSP) ^(L) signal to generated the So_(LSP) ^(L) signal. 4.A non-linear digital-to-analog conversion (NDAC) method in an integratedcircuit, the method comprising: generating a non-linearMost-Significant-Portion (MSP) analog output signal (So_(MSP) ^(N)) thatis proportional to a MSP reference signal (Sr_(MSP)), and is responsiveto a bank of Most-Significant-Bits (MSBs) of a digital input word(Di_(MSP)); generating a linear Least-Significant-Portion (LSP) analogoutput signal (So_(LSP) ^(L)) that is proportional to a LSP referencesignal (Sr_(LSP)), and is responsive to a bank of Least-Significant-Bits(LSBs) of a digital word (Di_(LSP)), and is responsive to the Di_(MSP)word; combining the So_(MPS) ^(N) signal and the So_(LSP) ^(L) signal togenerate a non-linear analog output signal (So_(N)) that is proportionalto a reference signal (S_(R)), and is responsive to a digital word(D_(I)), wherein the So_(LSP) ^(L) signal is a straight-lineapproximation between non-linear segments of the (So_(MSP) ^(N)) signal;wherein the Sr_(MSP) signal, and the Sr_(LSP) signal, are eachproportional to the S_(R) signal; and wherein the D_(I) word iscomprised of the Di_(MSP) word and the Di_(LSP) word; generating atleast one (So_(MSP) ^(N)) by at least one non-linear MSPDigital-to-Analog Converter (DAC_(MSP) ^(N)); generating at least oneSo_(LSP) ^(L) by at least one linear LSP Digital-to-Analog Converter(DAC_(LSP) ^(L)); generating at least one So_(N) signal that isproportional to the reference signal (S_(R)), wherein the at least oneSo_(N) signal is responsive to at least one D_(i) word; wherein thereference network of each of the DAC_(MSP) ^(N) is comprised of asequence of non-linearly scaled MSP reference signals (Sr_(MSP) ^(N))that are proportional to the Sr_(MSP) signal; wherein the referencenetwork of each of the DAC_(LSP) ^(L) is comprised of a sequence ofscaled LSP reference signals (Sr_(LSP) ^(L)) that are proportional tothe Sr_(LSP) signal; wherein each of the sequence of Sr_(MSP) ^(N)signals is at least one of squarely weighted, logarithmically weighted,non-linearly weighted, and individually weighted; wherein each of thesequence of Sr_(LSP) ^(L) signals is at least one of binary weighted,linearly weighted, and individually weighted; and wherein each of thesequence of Sr_(MSP) ^(N) signals and each of the sequence of Sr_(LSP)^(L) signals are biased from a common reference bias network (RBN). 5.The non-linear digital-to-analog conversion (NDAC) method in anintegrated circuit of claim 4, the method further comprising: wherein aplurality of the at least one So_(N) signal has a square profile;wherein a p-channel So_(N) signal, of the plurality of So_(N) signals,is responsive to a p-channel D word; wherein a q-channel So_(N) signal,of the plurality of So_(N) signals, is responsive to a q-channel D word;wherein the p-channel So_(N) and the q-channel So_(N) signals aresubtracted from one another to generate a scaled So_(xy) signal; whereinthe p-channel D word is comprised of a scaled X digital word and ascaled Y digital word that are added to one another; wherein theq-channel D word is comprised of a scaled Y digital word and a scaled Ydigital word that are subtracted from one another; and wherein thescaled So_(XY) signal is proportional to the S_(R), and is an analogrepresentation of a scaled multiplication product of the scaled Xdigital word and the scaled Y digital word.
 6. A non-lineardigital-to-analog converter (NDAC) system in an integrated circuit, thesystem comprising: a first non-linear Digital-to-Analog-Converter(DAC_(QM)), the DAC_(QM) comprised of a digital input port (D_(QM)), ananalog output port (Ao_(QM)), and an analog reference input port(Ar_(QM)); a first linear Digital-to-Analog-Converter (DAC_(1L)), theDAC_(1L) comprised of a digital input port (D_(1L)), an analog outputport (Ao_(1L)), and an analog reference input port (Ar_(1L)); a secondlinear Digital-to-Analog-Converter (DAC_(2L)), the DAC_(2L) comprised ofa digital input port (D_(2L)), an analog output port (Ao_(2L)), and ananalog reference input port (Ar_(2L)); a digital input word (D)comprised of a Most-Significant-Bits (MSB)s bank word (D_(MSP)), and aLeast-Significant-Bits (LSB)s bank word (D_(LSP)); a digital multiplier(X_(ML)), the X_(ML) comprised of an M input digital word port (M), an Ninput digital word port (N), and an output digital word port (M×N); theM port for receiving the D_(MSP) bank word; the N port for receiving theD_(LSP) bank word; the D_(1L) port coupled to the output digital wordport M×N; the D_(2L) port coupled to the digital word N port; the D_(QM)port coupled to the digital word M port; wherein the Ar_(QM) port forreceiving a first reference signal (Sr_(QM)); wherein the Ar_(1L) portfor receiving a second reference signal (Sr_(1L)); wherein the Ar_(2L)port for receiving a third reference signal (Sr_(2L)); wherein a sum ofsignals at the Ao_(1L) and Ao_(2L) ports is a straight-lineapproximation between non-linear segments of a signal at the Ao_(QM)port; wherein a sum of signals at the Ao_(QM), Ao_(1L), and Ao_(2L)ports generates a non-linear analog output signal (So_(N)) at an analogoutput port Ao_(N); wherein an analog reference signal (S_(R)) isproportionally scaled to the Sr_(QM), the Sr_(1L), and the Sr_(2L)signals; wherein a sequence of non-linear reference signals (Sr_(MSP)^(N)), which form a transfer function of the DAC_(QM), are proportionalto the S_(R) signal; wherein the sequence of Sr_(MSP) ^(N) signals areat least one of squarely weighted, logarithmically weighted,non-linearly weighted, and individually weighted; wherein a sequence oflinear reference signals (Sr_(LSP) ^(L)), which form a transfer functionof the DAC_(1L) and DAC_(2L), are proportional to the S_(R) signal;wherein the sequence of Sr_(LSP) ^(L) signals are at least one of binaryweighted, linearly weighted, and individually weighted; and wherein theSo_(N) signal substantially follows one of a square, logarithmic, andnon-linear profile, is proportional to the S_(R) signal, and responsiveto the D word.
 7. The non-linear digital-to-analog converter (NDAC)system in an integrated circuit of claim 6, the system furthercomprising: wherein the sequence of Sr_(MSP) ^(N) signals, and thesequence of Sr_(LSP) ^(L) signals, are biased from a common referencebias network (RBN).
 8. The non-linear digital-to-analog converter (NDAC)system in an integrated circuit of claim 6, the system furthercomprising: wherein a plurality of So_(N) signals following a squareprofile; wherein a p-channel So_(N) signal, of the plurality of So_(N)signals, is responsive to a p-channel D word; wherein a q-channel So_(N)signal, of the plurality of So_(N) signals, is responsive to a q-channelD word; wherein the p-channel So_(N) and the q-channel So_(N) signalsare subtracted from one another to generate a scaled So_(xy) signal;wherein the p-channel D word is comprised of a scaled X digital word anda scaled Y digital word that are added to one another; wherein theq-channel D word is comprised of a scaled Y digital word and a scaled Ydigital word that are subtracted from one another; and wherein thescaled So_(xy) signal is proportional to the S_(R), and is an analogrepresentation of a scaled multiplication product of the scaled Xdigital word and the scaled Y digital word.
 9. The non-lineardigital-to-analog converter (NDAC) system in an integrated circuit ofclaim 6, the system further comprising: the Ao_(QM) port, Ao_(1L) port,and Ao_(2L) port are coupled to an output port Ao_(Q); and wherein theDAC_(QM), DAC_(1L), and DAC_(2L) operate in current mode.
 10. Anon-linear digital-to-analog converter (NDAC) system in an integratedcircuit, the system comprising: a first non-lineardigital-to-analog-converter (DAC_(QM)), the DAC_(QM) comprised of adigital input port (D_(QM)), an analog output port (Ao_(QM)), and ananalog reference input port (Ar_(QM)); a first lineardigital-to-analog-converter (DAC_(1L)), the DAC_(1L) comprised of adigital input port (D_(1L)), an analog output port (Ao_(1L)), and ananalog reference input port (Ar_(1L)); a second lineardigital-to-analog-converter (DAC_(2L)), the DAC_(2L) comprised of adigital input port (D_(2L)), an analog output port (Ao_(2L)), and ananalog reference input port (Ar_(2L)); a digital input word (D)comprised of a Most-Significant-Bits (MSB)s bank word (D_(MSP)) and aLeast-Significant-Bits (LSB)s bank word (D_(LSP)); an MSB bank port (M)for receiving the D_(MSP) word; an LSB bank port (N) for receiving theD_(LSP) word; the D_(1L) port coupled to the M port; the D_(2L) portcoupled to the N port; the D_(QM) port coupled to the M port; whereinthe Ar_(QM) port for receiving a first reference signal (Sr_(QM));wherein the Ar_(1L) port for receiving a second reference signal(Sr_(1L)); wherein a signal at the Ao_(1L) port (So_(1L)) combined witha third reference offset signal (Sfr_(2L)) for being received by theAr_(2L) port; wherein a signal at the Ao_(1L) port is a straight-lineapproximation between non-linear segments of a signal at the Ao_(QM)port; wherein a sum of signals at the Ao_(QM) and the Ao_(1L) portsgenerates a non-linear analog output signal (So_(N)) at an analog outputport Ao_(N); wherein an analog reference signal (S_(r)) isproportionally scaled to the Sr_(QM), the Sr_(1L), and the Sr_(2L)signals; wherein a sequence of non-linear reference signals (Sr_(MSP)^(N)), which form the transfer function of the DAC_(QM), areproportional to the S_(R) signal; wherein the sequence of Sr_(MSP) ^(N)signals are at least one of squarely weighted, logarithmically weighted,non-linearly weighted, and individually weighted; wherein the sequenceof linear reference signals (Sr_(LSP) ^(L)), which form the transferfunction of the DAC_(1L) are proportional to the S_(R) signal; whereinthe sequence of Sr_(LSP) ^(L) signals are at least one of binaryweighted, linearly weighted, and individually weighted; and wherein theSo_(N) signal substantially follows one of a square, logarithmic, andnon-linear profile, is proportional to the S_(R) signal, and responsiveto the D word.
 11. The non-linear digital-to-analog converter (NDAC)system in an integrated circuit of claim 10, the system furthercomprising: wherein each of the sequence of Sr_(MSP) ^(N) signals, andeach of the sequence of Sr1 _(LSP) ^(L) signals are biased from a commonreference bias network (RBN).
 12. The non-linear digital-to-analogconverter (NDAC) system in an integrated circuit of claim 10, the systemfurther comprising: wherein a plurality of So_(N) signals following asquare profile; wherein a p-channel So_(N) signal, of the plurality ofSo_(N) signals, is responsive to a p-channel D word; wherein a q-channelSo_(N) signal, of the plurality of So_(N) signals, is responsive to aq-channel D word; wherein the p-channel So_(N) and the q-channel So_(N)signals are subtracted from one another to generate a scaled So_(xy)signal; wherein the p-channel D word is comprised of a scaled X digitalword and a scaled Y digital word that are added to one another; whereinthe q-channel D word is comprised of a scaled Y digital word and ascaled Y digital word that are subtracted from one another; and whereinthe scaled So_(xy) signal is proportional to the S_(R) and is an analogrepresentation of a scaled multiplication product of the scaled Xdigital word and the scaled Y digital word.
 13. The non-lineardigital-to-analog converter (NDAC) system in an integrated circuit ofclaim 10, the system further comprising: the Ao_(QM) port and Ao_(2L)port are coupled to an output port Ao_(Q); and wherein the DAC_(QM),DAC_(1L), and DAC_(2L) operate in current mode.